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Computer System Structures

cz:Struktury počítačových systémů

Lecturer: Richard Šusta richard@susta.cz, susta@fel.cvut.cz,

+420 2 2435 7359

ČVUT-FEL in Prague, CR – subject A0B35SPS

Version: 1.0

ECE 545 – Introduction to VHDL

Specifying time in VHDL

Picture: https://commons.wikimedia.org

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Units of time Unit Definition

Base Unit

fs femtoseconds (10-15 seconds)

Derived Units

ps picoseconds (10-12 seconds)

ns nanoseconds (10-9 seconds)

us microseconds (10-6 seconds)

ms miliseconds (10-3 seconds)

sec seconds

min minutes (60 seconds)

hr hours (3600 seconds)

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Physical data types

TIME is the only predefined physical data type,

Note: Types representing physical quantities, such as time,

voltage, capacitance, etc. are referred in VHDL as physical

data types.

Value of the physical data type is called a physical literal

and it can be an integer or a floating point number.

Numeric value and dimension MUST be separated by a

space. Numeric value of time is optional. If not given, 1 is

implied.

Smallest available resolution in VHDL is 1 fs.

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Examples

7 ns

1 min

min

12.65 us

978 fs

Unit of time

(dimension)

Space Numeric value

5

Arithmetic operations on TIME

Examples:

7 ns + 10 ns = 17 ns

1.2 ns – 12.6 ps = 1187400 fs

5 ns * 4.3 = 21.5 ns

20 ns / 5ns = 4

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ECE 545 – Introduction to VHDL

"Sensitivity list" ≡ "wait on!

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process(a,b)

begin

-- some statements, e.g.

y<=a and b;

end process;

process

begin

-- some statements, e.g.

y<=a and b;

wait on a, b;

end process;

a b

y Function

Until a or b inputs are unchanged,

y remains the same

<- the property of combinational circuits

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Quartus

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process(a,b)

begin

-- some statements, e.g.

y<=a and b;

end process;

process

begin

-- some statements, e.g.

y<=a and b;

wait on a, b;

end process;

• Assembling the circuit from the code is not an easy task, so synthesis

tools allow only a subset of VHDL.

• Quartus here requires sensitivity list - but remember that sensitivity

lists are not analogous to parameters of functions, but only another

form how to specify waiting condition for signal changes, clearer

relocations of "wait on" statements to the beginning of processes.

VHDL Wait Statements in simulation

Four possible kinds of wait-statements:

• wait on signal list;

wait until signal changes;

e.g.: wait on a;

• wait until condition;

wait until condition is met;

e.g.: wait until c='1';

• wait for duration;

wait for specified amount of time;

e.g.: wait for 10 ns;

• wait;

suspend indefinitely

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ECE 545 – Introduction to VHDL

Example

variable - signals

SPS 12

Example:

Design AND gate that can be switched by input

isNand to NAND.

a b

isNand='0'

y a b

isNand='1'

y

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SPS 13

Solution P

The task can be solved easily

a) e.g. by equation:

y <= (a and b) xor isNand;

b) or by multiplexer:

y <= a and b when isNand='0' else

not (a and b);

Picture: http://en.patmat.cz/

but student PAT has decided to

use process to test it.

SPS 14

Entity definition

library ieee; use ieee.std_logic_1164.all;

entity n2and is

port (a, b, isNand: in std_logic;

y : out std_logic);

end entity;

a

b

isNand

y

n2and

inst

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SPS 15

P-solution with variable

architecture dataflow of n2and is

begin

process(a,b, isNand)

variable tmp : std_logic;

begin

tmp:=a and b;

if isNand='1' then tmp:=not tmp; end if;

y<=tmp;

end process;

end architecture;

SPS 16

P-result

Comment: Quartus convert multiple assignment of variables to unique

assignments by introducing auxiliary internal variables tmp~ 0 and tmp~1.

Appendix: Character ~ is reserved only for names generated by the compiler,

it cannot be used in code.

isNand

y

0 a

b 1

Principle schema

tmp~0

tmp~1

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SPS 17

Simulation

and nand

SPS 18

Variables

Eng: VHDL reference:

The immediate assignment, notion : = , takes effect

immediately without any time dimension (i.e. without

propagation delay). The behavior of variable

assignments are just like that of a regular variable

assignments used in traditional programming

languages.

Consequence: The value that you assign to

variables in the code of a process we can

immediately read..

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SPS 19

Řešení M

Mat did not like Pat's solution and he

has reorganized the code using signals.

Signal - it does sound better

than some variable :-)

Picture: http://en.patmat.cz/

SPS 20

Wrong solution- the circuit got MAT

architecture dataflow of n2and is

signal tmp : std_logic;

begin

process(a,b, isNand)

begin

tmp<=a and b;

if isNand='1' then tmp<=not tmp; end if;

y<=tmp;

end process;

end architecture;

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SPS 21

Wrong result

Warning (332125): Found combinational loop of 2 nodes

isNand

y

0 a

b 1

Principle schema

tmp~0

tmp~1

SPS 22

Simulation

"Functional simulation" failed -> buffer overflow

"Timing-simulation" with propagation delay of gate

give result with oscilations

y

Time

y

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George Mason University ECE 545 – Introduction to VHDL

Pat dicoved Assignments

blocking :=

+ non-blocking <=

2 Kinds of Assignments

Variable assignments (blocking, immediate)

Syntax:

variable := expression;

Signal assignments (non-blocking, delta-cycle)

Syntax: signal <= expression;

signal <= expression after delay;

signal <= transport expression after delay;

signal <= reject time inertial expression after delay;

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Transport Delay

signal <= transport expression after delay;

This corresponds to models for simple wires

Pulses will be propagated, no matter how short they are.

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Transport Delay

Example:

c <= transport a or b after 10 ns;

1 a

b y

OR gate

a b

y

Pulse of 5 ns

20

40

60

80

ns

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a or b

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Inertial Delay

Suppression of all “spikes” shorter than the delay. By

default, inertial delay is assumed as "after" parameter

to model the behavior of gates.

• To switch state, gates require that input pulse

cross a certain threshold and remain unchanged

for a certain period of time (hold time).

• If the pulse is small, the gate will not change state.

• The minimum pulse width for an input pulse to

cause a change in state for a gate is called the

inertial delay of the gate

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Inertial Delay

Example

5 ns pulz is suppressed

c <= a or b after 10 ns; c <= INERTIAL a or b after 10 ns;

c <= REJECT 10 ns INERTIAL a or b after 10 ns;

equivalent

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a b

y

20

40

60

80

ns

a or b

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SPS 29

Signals

VHDL Reference:

In contrast to variables, the values assigned to

signals can be read back only after at least a

delta cycle (δ) time, infinitesimally small

advance in time - i.e. in reality, a signal is

updated during the next evaluation of the

process.

Delta Delay

If we write statement

output <= ‘0’;

it will be processed as

output <= ‘0’ after δ;

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In the code for the synthesis, the after keyword can never

appear - The exact time delay cannot be realized. Compiler

however will assemble all "<=" assignments as equivalents

after δ; where delta represents an infinitesimal delay.

Note: δ represents an imaginary internal compiler symbol,

a user's code cannot use it

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SPS 31

Signaly

You can imagine situation as a circuit, where signals (wires) contain

input values of the circuit and we only assign them new output

values.

x_signal

our code

new value

propagation delay

of a circuit

If a signal is only used within a process and it is not read by any

other process, it can be replaced by a variable. Variable have

advantage of limited (localized) scope, which in general is a good

thing.

Remember that signals are only one reasonable way for

interconnecting more processes or circuits, i.e. transfer values

from one process or circuit to another.

SPS 32

Pat made finally this correction

architecture dataflow of n2and is

signal tmp : std_logic;

begin

process(a,b, isNand)

begin

tmp<=a and b;

if isNand='1' then tmp<=not (a and b); end if;

y<=tmp;

end process;

end architecture;

P-code does not use the value assigned to tmp signal

inside of the process - the new value appears with delay.

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SPS 33

Result is again correct

SPS 34

How it will write others?

architecture dataflow of n2and is

begin

process(a, b, isNand)

begin

if isNand='1'

then y<=not (a and b);

else y<= a and b;

end if;

end process;

end architecture;

For example by this way - that is multiplexer

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George Mason University ECE 545 – Introduction to VHDL

Simulation in VHDL

better understanding of code

and time saving

TESTING OUR DESIGN…

by downloading our des ign in to machines

Vladimít Wagner, Ocelové město, 2010

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TESTBENCHES IN VHDL

Testing our design by

Found Not

Found

Our

intentions

Our design

Testbench for Errors Simulator

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Testing & simulation Formal Verification

Design

Under Test

Test vectors

Patterned vectors

System Model

Test properties

Test results

e.g.

hazard ...

True

or

False

Find

counter-example

Cannot cover all

possible cases

Possibility of surviving

subtle (corner case) bugs

Equivalent to simulating

all cases in simulation

No bug according to the

specified property

It is always possible Sometimes it is possible 38

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39

Simulation of PAT

SPS 40

Testbench

Our

design

inputs

ou

tpu

ts vhdl Testbench We can

automatically

compare results

with required

values.

stimuli written

in vhdl code

Our

design inputs

ou

tpu

ts

stimuli by

force commands (analogy to Vector

Wave Form file) graph

stimulus, pl. stimuli (from Latin stilus, stylus->style) - something that

rouses the mind or spirits or incites to activity - cz: podnět, stimul

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Keyword after in simulation

z <= ‘1’, ‘0’ after 5 ns, ‘1’ after 10 ns;

key0 <= ‘0’, ‘1’ after 30 ns; -- inicialization …

clk <= not clk after 5 ns; -- clocks

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0 5 10 15 20 25 30 35 40 ns

signal clk : std_logic:='0';

signal z, key0 : std_logic;

Note Initialized signals (wires), are

synthesized very difficult. Quartus often

refuses and writes about it just a

warning. Suitable only in simulation !!

z

clk

key0

42

library ieee; use ieee.std_logic_1164.all;

use ieee.numeric_std.all;

entity tb0 is -- entity for testbench does not contain declarations

end entity;

architecture testbench of tb0 is

component n2and is

port ( a, b, isNand : in std_logic; y : out std_logic );

end component;

signal x: unsigned(2 downto 0) := "000";

signal y, stop : std_logic;

begin

-- statements of architecture

end architecture;

testbench for Pat's program

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43

begin

x<= x+1 after 10 ns; -- x: unsigned(2 downto 0) := "000";

stop<='0', '1' after 320 ns; -- stop : std_logic;

in2and : n2and

port map( x(0), x(1), x(2), y ); -- (a,b,isNand,y)

assert stop /= '1'

report "Done!"

severity failure;

end architecture;

tb0 ekvivalent

and nand

- in reality, Quartus performs simulation by automatically

created testbench from "Vector Wave Form file".

is Quartus functional simulation for 320 ns

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DEMONSTRATION

OF MODELSIM ALTERA

Result of ModelSim simulation

46

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47 Fujita M: Introduction to VHDL, VDEC Tokyo 2005

Asserts & Reports

48 Fujita M: Introduction to VHDL, VDEC Tokyo 2005

Assert

Assert is a non-synthesizable statement

whose purpose is to write out messages

on the screen when problems are found

during simulation or synthesis.

Depending on the severity of the problem,

The simulator or compiler is instructed to

continue or halt.

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49 Fujita M: Introduction to VHDL, VDEC Tokyo 2005

Assert - syntax

ASSERT condition

[REPORT "message"]

[SEVERITY severity_level ];

The message is written when the condition

is FALSE.

Severity_level can be:

Note, Warning, Error (default), or Failure.

50 Fujita M: Introduction to VHDL, VDEC Tokyo 2005

Assert - Examples

assert initial_value <= max_value

report "initial value is too large"

severity error;

assert packet_length > 0

report "Code defines empty packet length"

severity warning;

assert false

report "Initialization complete"

severity note;

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51 Fujita M: Introduction to VHDL, VDEC Tokyo 2005

Report - syntax

REPORT "message"

[SEVERITY severity_level ];

The message is always written.

Severity_level can be:

Note (default), Warning, Error, or Failure.

52 Fujita M: Introduction to VHDL, VDEC Tokyo 2005

Report - Examples

report "Initialization complete";

report "Current time = " & time'image(now);

report "Incorrect branch" severity error;

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53

Simulation of VGA

inputs easy

outputs difficult

SPS 54

VGA_HS

VGA_SYNC

VGA_BLANK

VGA_VS

VGA_ CLK

Generator

of VGA

synchro-

nization

DisplayLogic

Logic functions

of colors

VGA_R

VGA_G

VGA_B

task 2

VGA_ CLK

25 MHz

yro

w

xcolu

mn

10/8

10/8

10/8

10 10

VG

A r

egis

ter

10

10

10

VGA_HS

VGA_SYNC

VGA_BLANK

VGA_VS

VGA_ CLK

Setting 10 or 8 bit colors

2

size

Clk

AClrn

Inputs and outputs of VGA

Sto

rag

e o

f resu

lt into

file

constant

generator

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SPS 55

Inputs

-- Tested the size input of our DisplayLogic,

-- change from "00" to "11"

constant SIZE_SWITCH : std_logic_vector(1 downto 0) := "10";

signal CLK_25MHz175 : std_logic := '0';

constant CLOCK_PERIOD : time := 39.722 ns;

CLK_25MHz175 <= not CLK_25MHz175

after CLOCK_PERIOD / 2;

Possible solutions depended on the initialization of signal

SPS 56

Better CLK_25MHz175

clk_process : process

begin

--for 50 % of CLK_25MHz175 period is'0'.

CLK_25MHz175 <= '0';

wait for CLOCK_PERIOD/2;

--for next 50% of CLK_25MHz175 period is '1'.

CLK_25MHz175 <= '1';

wait for CLOCK_PERIOD/2;

end process;

signal CLK_25MHz175 : std_logic;

constant CLOCK_PERIOD : time := 39.722 ns;

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SPS 57

Input ACLRN

signal ACLRN_signal : std_logic;

-- Clear process generates ACLRN for 1 CLOCK_PERIOD.

clear_process :process

begin

ACLRN_signal <= '0';

wait for CLOCK_PERIOD;

ACLRN_signal <= '1';

wait; -- wait forever => terminate process

end process;

DEMONSTRATION

OF MODELSIM ALTERA