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Simulation of Multiple Gate FinFET Device Gate Capacitance and Performance with Gate Length and Pitch Scaling Hui Zhao', Naveen Agrawal', Ramos Javier2, Subhash C. Rustagi3, M. Jurczak2, Yee-Chia Yeo', Ganesh S. Samudra', [1] Silicon Nano Device Laboratory (SNDL), ECE Department, National University of Singapore, Singapore. Email: [2] IMEC, Kapeldreef75, Heverlee, Belgium [3] Institute of Microelectronics, Singapore Science Park II, 2 Science Park Road, Singapore Abstract- In this work, we simulate silicon-on-insulator (SOI) multiple gate FinFET (MuGFET) with the design targeting for the ITRS 2004 specifications for NMOSFET. A detailed fully 3D simulation and analysis of the parasitic capacitances is performed for the first time to study the impact of scaling and pitch spacing. Unlike planar devices, FinFET scaling does not always result in a straightforward performance improvement due to the current crowding effect and series resistance. Keywords-Multi-gate; FinFET; capacitance; scaling; 3D simulation I. INTRODUCTION II. 3D PROCESS SIMULATION AND DEVICE BENCHMARKING A. 3D Process Simulation A 3D process simulation was performed in TaurusTM emulating the full fabrication process. Key physical effects such as angle implantation, implantation damage, spike annealing, transient diffusion of dopants and defects are included [4]. Fig. 2 shows the MuGFET structure simulated by TaurusTM. Two Arsenic implantations and one Phosphorous implantation were used for the source/drain doping and LDD formation [5]. Fig. 3 shows the 2D cut through middle of fin and source/drain, plotting As and P doping profile. MuGFET devices are suitable in sub-32 nm technology due to their excellent immunity to short channel effects and negligible junction capacitance which significantly reduces circuit delay [1]. However, in sub-iOOnm technologies, the effective capacitances do not reduce as predicted by the ITRS [2] because the parasitic capacitances do not scale as effectively. It was even reported in literature that when device is scaled beyond 18nm gate length, parasitic capacitances start dominating the effective capacitance [3]. To fully capture the scaling properties, one has to take the non-planar nature of the device geometry into account. As shown in the Cgs plot in Fig. 1, 2D simulation clearly overestimate the capacitance by ignoring the underlying bottom oxide layer and assuming that the device extends infinitely in the z-direction. In this work, full 3D device structure and doping profiles are incorporated for capacitance calculation. State-of-the-art process and device numerical simulator TaurusTM is used for forning the structure [4] and for capacitance extraction. The device prototype was then benchmarked with fabricated device from IMEC. With the use of calibrated and realistic physical device models, this work offers useful insights into the scaling properties of sub- 1 OOnm MuGFET device. In addition, the effect of fin pitch for multi fin device is also studied. 2.5 - 2.0 - 1.5 - LL 0 - I.- 1.0 - 0.5 - 0.0 - aOO_ II 0.0 0.2 0.4 0.6 Vg (V) -°-2D -o-3D 0.8 1.0 Fig. 1: 2D model over predict the gate-source capacitance Fig.2: MuGFET structure simulated by Taurus 3D 1-4244-0404-5/06/$20.00 © 2006 IEEE SISPAD 2006 252

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Page 1: Simulation Multiple Gate Capacitance andPerformance ...in4.iue.tuwien.ac.at/pdfs/sispad2006/pdfs/04061626.pdf · The Gaussian doping and gate stack parameters were fine tuned based

Simulation of Multiple Gate FinFET Device GateCapacitance and Performance

with Gate Length and Pitch Scaling

Hui Zhao', Naveen Agrawal', Ramos Javier2, Subhash C. Rustagi3, M. Jurczak2, Yee-Chia Yeo', Ganesh S. Samudra',[1] Silicon Nano Device Laboratory (SNDL), ECE Department, National University of Singapore, Singapore. Email:

[2] IMEC, Kapeldreef75, Heverlee, Belgium[3] Institute of Microelectronics, Singapore Science Park II, 2 Science Park Road, Singapore

Abstract- In this work, we simulate silicon-on-insulator (SOI)multiple gate FinFET (MuGFET) with the design targeting forthe ITRS 2004 specifications for NMOSFET. A detailed fully 3Dsimulation and analysis of the parasitic capacitances is performedfor the first time to study the impact of scaling and pitch spacing.Unlike planar devices, FinFET scaling does not always result in astraightforward performance improvement due to the currentcrowding effect and series resistance.

Keywords-Multi-gate; FinFET; capacitance; scaling; 3Dsimulation

I. INTRODUCTION

II. 3D PROCESS SIMULATION AND DEVICEBENCHMARKING

A. 3D Process SimulationA 3D process simulation was performed in TaurusTM

emulating the full fabrication process. Key physical effectssuch as angle implantation, implantation damage, spikeannealing, transient diffusion of dopants and defects areincluded [4]. Fig. 2 shows the MuGFET structure simulated byTaurusTM. Two Arsenic implantations and one Phosphorousimplantation were used for the source/drain doping and LDDformation [5]. Fig. 3 shows the 2D cut through middle of finand source/drain, plotting As and P doping profile.

MuGFET devices are suitable in sub-32 nm technology dueto their excellent immunity to short channel effects andnegligible junction capacitance which significantly reducescircuit delay [1]. However, in sub-iOOnm technologies, theeffective capacitances do not reduce as predicted by the ITRS[2] because the parasitic capacitances do not scale aseffectively. It was even reported in literature that when deviceis scaled beyond 18nm gate length, parasitic capacitances startdominating the effective capacitance [3]. To fully capture thescaling properties, one has to take the non-planar nature of thedevice geometry into account. As shown in the Cgs plot in Fig.1, 2D simulation clearly overestimate the capacitance byignoring the underlying bottom oxide layer and assuming thatthe device extends infinitely in the z-direction. In this work,full 3D device structure and doping profiles are incorporatedfor capacitance calculation. State-of-the-art process and devicenumerical simulator TaurusTM is used for forning the structure[4] and for capacitance extraction. The device prototype wasthen benchmarked with fabricated device from IMEC. With theuse of calibrated and realistic physical device models, thiswork offers useful insights into the scaling properties of sub-1OOnm MuGFET device. In addition, the effect of fin pitch formulti fin device is also studied.

2.5 -

2.0 -

1.5 -

LL

0 -I.- 1.0 -

0.5 -

0.0 -aOO_

II0.0 0.2 0.4 0.6

Vg (V)

-°-2D-o-3D

0.8 1.0

Fig. 1: 2D model over predict the gate-source capacitance

Fig.2: MuGFET structure simulated by Taurus 3D

1-4244-0404-5/06/$20.00 © 2006 IEEESISPAD 2006 252

Page 2: Simulation Multiple Gate Capacitance andPerformance ...in4.iue.tuwien.ac.at/pdfs/sispad2006/pdfs/04061626.pdf · The Gaussian doping and gate stack parameters were fine tuned based

A ~! I,i VeA I t E!IAi

(a)

tAXtlv1iJ IL 1.ttU 4Y

agreement with 3D simulated structure in the regime withdoping above lol cm-3 while simulation efficiency andconvergence were greatly improved. The extracted dopingprofile and the fitted Gaussian profile are shown in Fig. 4.

The Gaussian doping and gate stack parameters were finetuned based on experimental results and measurements. Anovel gate stack was used in the device [7]. The work functionand dielectric thickness was extracted by matching the gatecapacitance of a sample fabricated device. An excellent fit wasachieved by having 4 nm high-k dielectric and 4.75 eV workfunction for the gate (Fig. 5). The doping profile was then fine-tuned iteratively by fitting the simulated drain and gateelectrical characteristics with experiment results. The devicesimulation included quantum effect, advanced mobility andrecombination models [6]. Simulated and measured Ir Vgcurves are shown in Fig. 6.

2.50E-014 -

2.OOE-014 -

H 1 50E-014 -

C) 1.00E-014-

5.OOE-015 -

O.OOE+000 -

(b)Fig.3: Active (a) As profile and (b) P profile plotted on 2D cut fromprocess simulation

simulation* measurement

I * E U

-1 0Vg (V)

(a)

(b)Fig.4: Active (a) As (b) P profile plotted on 2D cut at the fin centerusing Gaussian fitting

B. Bechmarking with Measurment DataIt is not possible to use an iterative process simulation to fit

measurement data due to the formidable CPU time. Instead, thedoping profile was fitted using a linear combination ofGaussians while maintaining the simulated structure. Thismethod reproduces the profile with reasonable accuracy in

Fig.5: Gate work function and dielectric thickness fitting using C-Vmeasurement data

Measurement Vd=0 1V500 - o Measurement Vd=0 3V A

_ A Measurement V IV400 - - Simulation Vd=0 1V t/

--Simulation Vd=0.3V A/300 -d'

E Simu lation Vd=1v V A i

<200-

- 100 -

0.0 0.2 0.4 0.6 0.8 1.0Vg (V)

Fig. 6: Calibrated device gate characteristicBlue: fabricated MuGFET, green: device physical model

III. RESULTS AND DISCUSSION

A. Inversion Charge Distibution ExtractionThe inversion charge distribution for two devices of

different gate lengths (Lg) and fin widths (Tfn) are plotted inFig. 7 at different gate biases. Volume inversion with a singlecharge centroid at center of fin occurs for gate bias up to 0.5 V.As the gate voltage increases further, the centroid starts to splitinto two and moves towards the each of the fin sidewall surface

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1

SISPAD 2006 253

Page 3: Simulation Multiple Gate Capacitance andPerformance ...in4.iue.tuwien.ac.at/pdfs/sispad2006/pdfs/04061626.pdf · The Gaussian doping and gate stack parameters were fine tuned based

while the inversion charge density at the fin center remainsrelatively stable at a saturation value. It is clear that for finwidth down to 8 nm the volume inversion indeed contributed tothe superior turn-on performance in sub-threshold regime asdescribed in the literature [8] but not after strong inversion. Theplot also shows that the device with a thinner fin in which gatecoupling is stronger has higher inversion charge density instrong inversion and its charge peaks are further from channelsurface. This will also have a positive effect on current drivedue to less surface roughness scattering.

1.5-1.4-1.3-1.2-1.1-

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06-0-) 0.6-0.50.4-0.30.2

0.0

V

C

-

(.0

Si Lg-45nm,Tilfn=20nm

A -1.0.1 .00

*S3:Lg-13nmT in=8nm

0.00Y' (um) *1 02

1 .O0

-LLU-

-0

0.45 -

0.40 -

0.35 -

0.30 -

0.25 -

0.20 -

S-SiS2S3S4

0.2 0.4 0.6 0.8

Vg (V)

(a)

S

-A-S25-oS3

-R-S4

Iz

0.0 0.2 0.4 0.6 0.8

Vg (V)

Fig.7: Electron density plotted along fin cross section at Vg=O.1, 0.2, 0.5,0.9vSI: Lg-45nm, Tfi,=20nm S2: Lg-13nm, Tfi,=8nm (y-axis is along thechannel width)

B. Scaling Properties ofMuGFETsThe calibrated device is scaled based on ITRS projections.

The device specifications are described in Table 1.The capacitance was extracted using AC device simulation.

Fig 8 plots the Cg, and Cgd (in fF/um). Increase of capacitancedue to To, reduction is only seen for device with fin widthlarger than 10 nm. This is predictable since volume inversion ismore prominent in very thin channel and the charge peaks arefurther moved inside the fin. However, this advantage ofsmaller capacitance does not result in better speed because ofthe significantly larger series resistance. This is reflected by theCV/I curve in Fig 9 which shows the fastest device is in fact S2with gate length of 35 nm (Leff 25 nm). We can conclude thataggressive scaling of a multiple gate device may not result inmuch incentive in terms of current and delay though thereduced capacitance can be useful for some applications.

Table 1: Scaled device detail

Printed High-k Fin FinLg Dielectric Length Width (nm)(nm) Thickness (nm) (nm) (nm)

Calibrated Device S 60 4 260 20 60Scaled Device Si 45 3 200 15 45Scaled Device S2 35 2.5 180 13 40Scaled Device S3 25 2 120 10 30Scaled Device S4 18 2 100 8 25

(b)Fig.8: (a) Cg, (b) Cgd as a function of Vg for various scaled singlefin device at Vd=0.8V

3.0 -

2.8 -

2.6 -

2.4 -

u)' 2.2 -

30-

2.0 -

o 1.8-1.6 -

1.4 -

1.2 -

1.U+

Si

SS4 S3

S2

10 20 30 40Lg(nm)

50 60

Fig.9: Estimated delay for scaled single fin device of various gatelength (Vd-0.8V)

C. Pitch Effect ofMulti-fin MuGFETDue to aspect ratio constraint, the current drive of single fin

is often too small for circuit application, thus multi-finstructure is more useful and practical. However, puttingconducting channels in close proximity produces strongerfringing field affecting capacitance and channel chargedistribution. These effects need to be carefully studied.

In the case of a wider fin width device, we found that as thefins are placed closer to each other the channel chargedistribution is changed. Charge peaks actually shift from inside

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Page 4: Simulation Multiple Gate Capacitance andPerformance ...in4.iue.tuwien.ac.at/pdfs/sispad2006/pdfs/04061626.pdf · The Gaussian doping and gate stack parameters were fine tuned based

the fin towards the fin surface and the number of inversioncarriers available in the channel increases as shown in Fig. 10(a). This shifting of electron peaks signals the formation of alarger gate field and reduction of dielectric EOT which bothresult in higher Cg, and Cgd. This trend can be clearly observedin Fig. 11 (a). Saturation current is found to increase by about6%. As plotted in Fig. 12, over all normalized delay time isincreased by -25% as the pitch is reduced to less than 100nmas comparing with that of a single fin (approximately representthe case of infinite pitch).

However, devices of very thin fin width exhibitcharacteristic which is opposite to the above described (bothCgd and Cgs). In a multi-fin structure of Wfp,=8nm, the channelinversion charge is found to be independent of pitch as shownin Fig. 10 (b). In this case, the change in capacitance isdominated by the strong fringing field from gate to source anddrain. Due to the larger source/drain region required for higherpitch device, both Cg, and Cgd are larger as shown in Fig. 11(b).

Z,04)0wt

4L

, - Pitch=50nm

Pitch= 100nm

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1 .00-50 60 70 80 90 100

Pitch (nm)

(a)

0.60-

0.55-

U- 0.500 .-

0.45-

20 30 40Pitch (nm)

Lff=1 8nmWf =8nm

50

(b)Fig.11: Saturation Cgs against pitch for MuGFET with (a) fin widthof20nm (b) fin width of 8nm (both simulated at Vg Va=0.8V)

2.75 -

2.50 -

- 2.25 -

2.00 -

-0-Multi-Fin Device with different pitch-- Single Fin Device (-infinite pitch)

A40 60 80 100 120 140 160 180 200

pitch (nm)

2E1 '.ED 1.5E1'

U,

° 1E1'in0 lla)LU

.o

a)C:

Pitch 25nm, Vg=0.2VPitch 25nm, Vg=0.6VPitch 25nm, Vg=0.8VPitch 35nm, Vg=0.2VPitch 35nm, Vg=0.6VPitch 35nm, Vg=0.8VPitch 50nm, Vg=0.2VPitch 50nm, Vg=0.6VPitch 50nm, Vg=0.8V

0.000 0.002 0.004 0.006 0.008

Distance along fin cross section (gm)

(b)Fig.10: Electron distribution in the channel for (a) multi finMuGFET with 20nm fin width and lOOnm and 50nm pitch at Vg =0.2 & 0.9V. (b) Multi fin MuGFET with 8nm fin width and 50nm,35nm, and 25nm pitch at Vg=0.2, 0.6, 0.8V. The devices haveLejp18nm, L1, =80nm and Wfi=8nm.

Fig.12: Estimated delay for multi-fin MuGFET with different finpitch (Vg 0.8v) Wfik=20nm, Lg=60nm

IV. CONCLUSION

AC analysis in 3D device simulations shows increase ingate capacitance when fin pitch decreases for wide fin (-20nm)and increase of capacitance in device with narrower and shorterfin. The delay performance, however, is relatively uniformonce the pitch is below 100nm. On the other hand, there is nomonotonic trend for Cg,lCgd of a single fin device on scaling.

REFERENCES[1] P. Yang et al., IEEE Trans. Computer-Aided Design Integr. Circuits

Syst., vol. CAD-1, 1982[2] International Technology Roadmap for Semiconductors 2005:

http://www.itrs.net/Common/20051TRS/Home2005.htm[3] V. Trivedi et al.. IEEE Electron Device Trans. Vol. 52, pp. 56-62, 2005[4] Taurus Process Manual, Synopsys Inc.[5] N. Collaert et al. IEEE International Conference on Integr. Circuit and

Tech. 2006, ppI87-189[6] Taurus Device Manual, Synopsys Inc.[7] Beckx et al. Microelectronics Reliability 45 (2005) 1007-1011.[8] F. Balestra et al. IEEE Electron Device Lett., vol. 8, pp. 410-412, 1987

1-4244-0404-5/06/$20.00 0 2006 IEEE

o4~Li.

SISPAD 2006 255