lectures recommandées : givone / sections 3.1 à 3 · transparent 2.3 2.1 – postulats et...

Transparent 21

21 ndash Postulats et theacuteoregravemes ELE1300 - CIRCUITS LOGIQUES

Chapitre II ndash Algegravebre booleacuteenne

Lectures recommandeacutees Givone sections 31 agrave 33

1854 - George Boole (1815-1864)

1938 - Claude Shannon (1916-2001)

Postulats principes premiers

Theacuteoregravemes expressions deacutemontrables

Axioms Lois non prouvables

Invente une eacutecriture algeacutebrique des formulations logiques

Applique lrsquoalgegravebre de Boole aux circuits (dits logiques)

Transparent 22


Chapitre II ndash Algegravebre booleacuteenne (suite)

Une algegravebre de Boole est la donneacutee de

bullun ensemble E

bulldeux eacuteleacutements particuliers de E 0 et 1(correspondant respectivement agrave FAUX et VRAI)

bulldeux opeacuterations binaires sur E + et (correspondant respectivement au OU et ET logiques)

bullune opeacuteration unaire sur E macr(correspondant agrave la neacutegation logique)

Transparent 23



Ces donneacutees veacuterifient les axiomes suivants soient a b et c des eacuteleacutements de E

bullCommutativiteacute a+b = b+a ab = ba

bullAssociativiteacute (a+b)+c = a+(b+c) (ab) c = a(bc)

bullDistributiviteacute a(b+c) = ab+ac a+(bc) = (a+b) (a+c)

bullEacuteleacutement neutre a+0 = a a1 = a

bullCompleacutementation a + a = 1 a a = 0

Transparent 24



Ce qui peut sembler inhabituel ici crsquoest






Transparent 25



Remarque le principe de dualiteacute srsquoapplique

changer les + pour des middot

changer les middot pour des +

changer les 0 pour des 1


Transparent 26



On admet les postulats suivants (tables de veacuteriteacute des opeacuterateurs)

P1 00 = 0

P2 01 = 0

P2bis 10 = 0

P3 11 = 1

P4 0+0 = 0

P5 0+1 = 1

P5bis 1+0 = 1

P6 1+1 = 1

P7

P8 01=10 =

Transparent 27



Principaux theacuteoregravemes

A A A+ = A A Asdot =

( )A A B A+ sdot = ( )A A B Asdot + =

( )A A B A B+ sdot = + ( )A A B A Bsdot + = sdot

( )A A=

(loi drsquoabsorption)

(idempotence)

(double neacutegation)

Transparent 28



Principaux theacuteoregravemes (suite)

( )A B A B+ = sdot( )A B A Bsdot = + (loi de DeMorgan)

Problegravemes suggeacutereacutes Givone 31 abe

(eacuteleacutements absorbants)11A =+ 00A =sdot

Transparent 29



On peut srsquoamuser agrave prouver certains theacuteoregravemes

A A A+ = A A Asdot = (idempotence)

( )A A B A+ sdot = ( )A A B Asdot + = (loi drsquoabsorption)


Transparent 210



Table de veacuteriteacute

1 2 i i nS f A A A=1 2 1

0 0 0 0 10 0 0 1 10 0 1 0 0

1 1 1 1 1

n n iA A A A SminusL

L

L

L

M M M M M

L

Un tableau qui illustre la correspondance entre lrsquoeacutetat drsquoune expressionlogique et la combinaison des eacutetats de ses variables

Transparent 211



Deux expressions logiques sont eacutegales

ssi leur table de veacuteriteacute sont identiques

( )A B A B+ = sdot( )A B A Bsdot = +

Exemple Loi de DeMorgan

Essayez de le faire analytiquement et vous aurez des migraines

Transparent 212

22 ndash Portes logiques ELE1300 - CIRCUITS LOGIQUES


A S

0 1

1 0

A S

INVERSEUR

S A=

Lectures recommandeacutees Givone sections 371 391

392 396 et 397 3 premiers paragraphes

Transparent 213



A B S

0 0 1

0 1 1

1 0 1

1 1 0

AB S

NON-ET(laquo NAND raquo)

S AB=

A B S

0 0 0

0 1 0

1 0 0

1 1 1

AB S

ET(laquo AND raquo)

ou S A B AB= sdot

(suite)

Transparent 214



A B S

0 0 1

0 1 0

1 0 0

1 1 0

S A B= +

A B S

0 0 0

0 1 1

1 0 1

1 1 1

AB S

OU(laquo OR raquo)

S A B= +

AB S

NON-OU(laquo NOR raquo)

Transparent 215



A B S

0 0 1

0 1 0

1 0 0

1 1 1

AB S

EacuteQUIVALENCE(laquo XNOR raquo)

A B S

0 0 0

0 1 1

1 0 1

1 1 0

AB S

OU EXCLUSIF(laquo XOR raquo)

S A B= oplus BABAS otimes=oplus=

Transparent 216



Portes logiques agrave entreacutees multiples

A1A2

An

A1A2

An

A1A2

An

A1A2

An

1 2 nS A A A= + + +L

1 2 nS A A A= + + +L

1 2 nS A A A= sdot sdot sdotL


Transparent 217

23 ndash Reacutealisation technique ELE1300 - CIRCUITS LOGIQUES


Lectures facultatives Givone section 310

Transparent 218



Exemple de circuit SN74LS00 (Texas Instruments httpfocusticomlitdssymlinksn74ls00pdf )

10

11

12

13

8

9

14

5

4

3

2

7

6

1A1

B1

S1

A2

B2

S2

A4

B4

S4

A3

B3

S3

VCC

GND

(suite)

Transparent 219



Autres exemples de circuits (Texas Instruments httpfocusticomlitugscyd013scyd013pdf )

SN74LS02

SN74LS04

SN74LS08

SN74LS10

SN74LS32

SN74LS86A

Transparent 220



SN74LS86A

Exemple drsquoapplication Production drsquoun bit de pariteacute (ou drsquoimpariteacute) associeacuteagrave un bloc de 4 bits

p

b1

b2

b3

b4

b1

b2

b3

b4

IMPARITEacute

PARITEacute5 volts

Transparent 221



Logique positive vs logique neacutegative

A B S

bas bas bas

bas haut bas

haut bas bas

haut haut haut

Soit une table de veacuteriteacute donneacutee relativement aux tensions

bas = tension basse (exemple 0 volt)haut = tension haute (exemple 5 volts)

Logique positive

bas = bit 0 haut = bit 1

La table deacutecrit une porte ET

AB S

Logique neacutegative


La table deacutecrit une porte OU

AB S

Transparent 22



Une algegravebre de Boole est la donneacutee de

bullun ensemble E

bulldeux eacuteleacutements particuliers de E 0 et 1(correspondant respectivement agrave FAUX et VRAI)

bulldeux opeacuterations binaires sur E + et (correspondant respectivement au OU et ET logiques)

bullune opeacuteration unaire sur E macr(correspondant agrave la neacutegation logique)

Transparent 23









Transparent 24









Transparent 25








Transparent 26




P1 00 = 0

P2 01 = 0

P2bis 10 = 0

P3 11 = 1

P4 0+0 = 0

P5 0+1 = 1

P5bis 1+0 = 1

P6 1+1 = 1

P7

P8 01=10 =

Transparent 27







( )A A=


(idempotence)


Transparent 28







Transparent 29







Transparent 210




1 2 i i nS f A A A=1 2 1

0 0 0 0 10 0 0 1 10 0 1 0 0

1 1 1 1 1


L

L

L

M M M M M

L


Transparent 211








Transparent 212



A S

0 1

1 0

A S

INVERSEUR

S A=



Transparent 213



A B S

0 0 1

0 1 1

1 0 1

1 1 0

AB S


S AB=

A B S

0 0 0

0 1 0

1 0 0

1 1 1

AB S

ET(laquo AND raquo)

ou S A B AB= sdot

(suite)

Transparent 214



A B S

0 0 1

0 1 0

1 0 0

1 1 0

S A B= +

A B S

0 0 0

0 1 1

1 0 1

1 1 1

AB S

OU(laquo OR raquo)

S A B= +

AB S


Transparent 215



A B S

0 0 1

0 1 0

1 0 0

1 1 1

AB S


A B S

0 0 0

0 1 1

1 0 1

1 1 0

AB S



Transparent 216




A1A2

An

A1A2

An

A1A2

An

A1A2

An

1 2 nS A A A= + + +L

1 2 nS A A A= + + +L



Transparent 217




Transparent 218




10

11

12

13

8

9

14

5

4

3

2

7

6

1A1

B1

S1

A2

B2

S2

A4

B4

S4

A3

B3

S3

VCC

GND

(suite)

Transparent 219




SN74LS02

SN74LS04

SN74LS08

SN74LS10

SN74LS32

SN74LS86A

Transparent 220



SN74LS86A


p

b1

b2

b3

b4

b1

b2

b3

b4

IMPARITEacute

PARITEacute5 volts

Transparent 221




A B S

bas bas bas

bas haut bas

haut bas bas

haut haut haut



Logique positive



AB S




AB S

Transparent 23









Transparent 24









Transparent 25








Transparent 26




P1 00 = 0

P2 01 = 0

P2bis 10 = 0

P3 11 = 1

P4 0+0 = 0

P5 0+1 = 1

P5bis 1+0 = 1

P6 1+1 = 1

P7

P8 01=10 =

Transparent 27







( )A A=


(idempotence)


Transparent 28







Transparent 29







Transparent 210




1 2 i i nS f A A A=1 2 1

0 0 0 0 10 0 0 1 10 0 1 0 0

1 1 1 1 1


L

L

L

M M M M M

L


Transparent 211








Transparent 212



A S

0 1

1 0

A S

INVERSEUR

S A=



Transparent 213



A B S

0 0 1

0 1 1

1 0 1

1 1 0

AB S


S AB=

A B S

0 0 0

0 1 0

1 0 0

1 1 1

AB S

ET(laquo AND raquo)

ou S A B AB= sdot

(suite)

Transparent 214



A B S

0 0 1

0 1 0

1 0 0

1 1 0

S A B= +

A B S

0 0 0

0 1 1

1 0 1

1 1 1

AB S

OU(laquo OR raquo)

S A B= +

AB S


Transparent 215



A B S

0 0 1

0 1 0

1 0 0

1 1 1

AB S


A B S

0 0 0

0 1 1

1 0 1

1 1 0

AB S



Transparent 216




A1A2

An

A1A2

An

A1A2

An

A1A2

An

1 2 nS A A A= + + +L

1 2 nS A A A= + + +L



Transparent 217




Transparent 218




10

11

12

13

8

9

14

5

4

3

2

7

6

1A1

B1

S1

A2

B2

S2

A4

B4

S4

A3

B3

S3

VCC

GND

(suite)

Transparent 219




SN74LS02

SN74LS04

SN74LS08

SN74LS10

SN74LS32

SN74LS86A

Transparent 220



SN74LS86A


p

b1

b2

b3

b4

b1

b2

b3

b4

IMPARITEacute

PARITEacute5 volts

Transparent 221




A B S

bas bas bas

bas haut bas

haut bas bas

haut haut haut



Logique positive



AB S




AB S

Transparent 24









Transparent 25








Transparent 26




P1 00 = 0

P2 01 = 0

P2bis 10 = 0

P3 11 = 1

P4 0+0 = 0

P5 0+1 = 1

P5bis 1+0 = 1

P6 1+1 = 1

P7

P8 01=10 =

Transparent 27







( )A A=


(idempotence)


Transparent 28







Transparent 29







Transparent 210




1 2 i i nS f A A A=1 2 1

0 0 0 0 10 0 0 1 10 0 1 0 0

1 1 1 1 1


L

L

L

M M M M M

L


Transparent 211








Transparent 212



A S

0 1

1 0

A S

INVERSEUR

S A=



Transparent 213



A B S

0 0 1

0 1 1

1 0 1

1 1 0

AB S


S AB=

A B S

0 0 0

0 1 0

1 0 0

1 1 1

AB S

ET(laquo AND raquo)

ou S A B AB= sdot

(suite)

Transparent 214



A B S

0 0 1

0 1 0

1 0 0

1 1 0

S A B= +

A B S

0 0 0

0 1 1

1 0 1

1 1 1

AB S

OU(laquo OR raquo)

S A B= +

AB S


Transparent 215



A B S

0 0 1

0 1 0

1 0 0

1 1 1

AB S


A B S

0 0 0

0 1 1

1 0 1

1 1 0

AB S



Transparent 216




A1A2

An

A1A2

An

A1A2

An

A1A2

An

1 2 nS A A A= + + +L

1 2 nS A A A= + + +L



Transparent 217




Transparent 218




10

11

12

13

8

9

14

5

4

3

2

7

6

1A1

B1

S1

A2

B2

S2

A4

B4

S4

A3

B3

S3

VCC

GND

(suite)

Transparent 219




SN74LS02

SN74LS04

SN74LS08

SN74LS10

SN74LS32

SN74LS86A

Transparent 220



SN74LS86A


p

b1

b2

b3

b4

b1

b2

b3

b4

IMPARITEacute

PARITEacute5 volts

Transparent 221




A B S

bas bas bas

bas haut bas

haut bas bas

haut haut haut



Logique positive



AB S




AB S

Transparent 25








Transparent 26




P1 00 = 0

P2 01 = 0

P2bis 10 = 0

P3 11 = 1

P4 0+0 = 0

P5 0+1 = 1

P5bis 1+0 = 1

P6 1+1 = 1

P7

P8 01=10 =

Transparent 27







( )A A=


(idempotence)


Transparent 28







Transparent 29







Transparent 210




1 2 i i nS f A A A=1 2 1

0 0 0 0 10 0 0 1 10 0 1 0 0

1 1 1 1 1


L

L

L

M M M M M

L


Transparent 211








Transparent 212



A S

0 1

1 0

A S

INVERSEUR

S A=



Transparent 213



A B S

0 0 1

0 1 1

1 0 1

1 1 0

AB S


S AB=

A B S

0 0 0

0 1 0

1 0 0

1 1 1

AB S

ET(laquo AND raquo)

ou S A B AB= sdot

(suite)

Transparent 214



A B S

0 0 1

0 1 0

1 0 0

1 1 0

S A B= +

A B S

0 0 0

0 1 1

1 0 1

1 1 1

AB S

OU(laquo OR raquo)

S A B= +

AB S


Transparent 215



A B S

0 0 1

0 1 0

1 0 0

1 1 1

AB S


A B S

0 0 0

0 1 1

1 0 1

1 1 0

AB S



Transparent 216




A1A2

An

A1A2

An

A1A2

An

A1A2

An

1 2 nS A A A= + + +L

1 2 nS A A A= + + +L



Transparent 217




Transparent 218




10

11

12

13

8

9

14

5

4

3

2

7

6

1A1

B1

S1

A2

B2

S2

A4

B4

S4

A3

B3

S3

VCC

GND

(suite)

Transparent 219




SN74LS02

SN74LS04

SN74LS08

SN74LS10

SN74LS32

SN74LS86A

Transparent 220



SN74LS86A


p

b1

b2

b3

b4

b1

b2

b3

b4

IMPARITEacute

PARITEacute5 volts

Transparent 221




A B S

bas bas bas

bas haut bas

haut bas bas

haut haut haut



Logique positive



AB S




AB S

Transparent 26




P1 00 = 0

P2 01 = 0

P2bis 10 = 0

P3 11 = 1

P4 0+0 = 0

P5 0+1 = 1

P5bis 1+0 = 1

P6 1+1 = 1

P7

P8 01=10 =

Transparent 27







( )A A=


(idempotence)


Transparent 28







Transparent 29







Transparent 210




1 2 i i nS f A A A=1 2 1

0 0 0 0 10 0 0 1 10 0 1 0 0

1 1 1 1 1


L

L

L

M M M M M

L


Transparent 211








Transparent 212



A S

0 1

1 0

A S

INVERSEUR

S A=



Transparent 213



A B S

0 0 1

0 1 1

1 0 1

1 1 0

AB S


S AB=

A B S

0 0 0

0 1 0

1 0 0

1 1 1

AB S

ET(laquo AND raquo)

ou S A B AB= sdot

(suite)

Transparent 214



A B S

0 0 1

0 1 0

1 0 0

1 1 0

S A B= +

A B S

0 0 0

0 1 1

1 0 1

1 1 1

AB S

OU(laquo OR raquo)

S A B= +

AB S


Transparent 215



A B S

0 0 1

0 1 0

1 0 0

1 1 1

AB S


A B S

0 0 0

0 1 1

1 0 1

1 1 0

AB S



Transparent 216




A1A2

An

A1A2

An

A1A2

An

A1A2

An

1 2 nS A A A= + + +L

1 2 nS A A A= + + +L



Transparent 217




Transparent 218




10

11

12

13

8

9

14

5

4

3

2

7

6

1A1

B1

S1

A2

B2

S2

A4

B4

S4

A3

B3

S3

VCC

GND

(suite)

Transparent 219




SN74LS02

SN74LS04

SN74LS08

SN74LS10

SN74LS32

SN74LS86A

Transparent 220



SN74LS86A


p

b1

b2

b3

b4

b1

b2

b3

b4

IMPARITEacute

PARITEacute5 volts

Transparent 221




A B S

bas bas bas

bas haut bas

haut bas bas

haut haut haut



Logique positive



AB S




AB S

Transparent 27







( )A A=


(idempotence)


Transparent 28







Transparent 29







Transparent 210




1 2 i i nS f A A A=1 2 1

0 0 0 0 10 0 0 1 10 0 1 0 0

1 1 1 1 1


L

L

L

M M M M M

L


Transparent 211








Transparent 212



A S

0 1

1 0

A S

INVERSEUR

S A=



Transparent 213



A B S

0 0 1

0 1 1

1 0 1

1 1 0

AB S


S AB=

A B S

0 0 0

0 1 0

1 0 0

1 1 1

AB S

ET(laquo AND raquo)

ou S A B AB= sdot

(suite)

Transparent 214



A B S

0 0 1

0 1 0

1 0 0

1 1 0

S A B= +

A B S

0 0 0

0 1 1

1 0 1

1 1 1

AB S

OU(laquo OR raquo)

S A B= +

AB S


Transparent 215



A B S

0 0 1

0 1 0

1 0 0

1 1 1

AB S


A B S

0 0 0

0 1 1

1 0 1

1 1 0

AB S



Transparent 216




A1A2

An

A1A2

An

A1A2

An

A1A2

An

1 2 nS A A A= + + +L

1 2 nS A A A= + + +L



Transparent 217




Transparent 218




10

11

12

13

8

9

14

5

4

3

2

7

6

1A1

B1

S1

A2

B2

S2

A4

B4

S4

A3

B3

S3

VCC

GND

(suite)

Transparent 219




SN74LS02

SN74LS04

SN74LS08

SN74LS10

SN74LS32

SN74LS86A

Transparent 220



SN74LS86A


p

b1

b2

b3

b4

b1

b2

b3

b4

IMPARITEacute

PARITEacute5 volts

Transparent 221




A B S

bas bas bas

bas haut bas

haut bas bas

haut haut haut



Logique positive



AB S




AB S

Transparent 28







Transparent 29







Transparent 210




1 2 i i nS f A A A=1 2 1

0 0 0 0 10 0 0 1 10 0 1 0 0

1 1 1 1 1


L

L

L

M M M M M

L


Transparent 211








Transparent 212



A S

0 1

1 0

A S

INVERSEUR

S A=



Transparent 213



A B S

0 0 1

0 1 1

1 0 1

1 1 0

AB S


S AB=

A B S

0 0 0

0 1 0

1 0 0

1 1 1

AB S

ET(laquo AND raquo)

ou S A B AB= sdot

(suite)

Transparent 214



A B S

0 0 1

0 1 0

1 0 0

1 1 0

S A B= +

A B S

0 0 0

0 1 1

1 0 1

1 1 1

AB S

OU(laquo OR raquo)

S A B= +

AB S


Transparent 215



A B S

0 0 1

0 1 0

1 0 0

1 1 1

AB S


A B S

0 0 0

0 1 1

1 0 1

1 1 0

AB S



Transparent 216




A1A2

An

A1A2

An

A1A2

An

A1A2

An

1 2 nS A A A= + + +L

1 2 nS A A A= + + +L



Transparent 217




Transparent 218




10

11

12

13

8

9

14

5

4

3

2

7

6

1A1

B1

S1

A2

B2

S2

A4

B4

S4

A3

B3

S3

VCC

GND

(suite)

Transparent 219




SN74LS02

SN74LS04

SN74LS08

SN74LS10

SN74LS32

SN74LS86A

Transparent 220



SN74LS86A


p

b1

b2

b3

b4

b1

b2

b3

b4

IMPARITEacute

PARITEacute5 volts

Transparent 221




A B S

bas bas bas

bas haut bas

haut bas bas

haut haut haut



Logique positive



AB S




AB S

Transparent 29







Transparent 210




1 2 i i nS f A A A=1 2 1

0 0 0 0 10 0 0 1 10 0 1 0 0

1 1 1 1 1


L

L

L

M M M M M

L


Transparent 211








Transparent 212



A S

0 1

1 0

A S

INVERSEUR

S A=



Transparent 213



A B S

0 0 1

0 1 1

1 0 1

1 1 0

AB S


S AB=

A B S

0 0 0

0 1 0

1 0 0

1 1 1

AB S

ET(laquo AND raquo)

ou S A B AB= sdot

(suite)

Transparent 214



A B S

0 0 1

0 1 0

1 0 0

1 1 0

S A B= +

A B S

0 0 0

0 1 1

1 0 1

1 1 1

AB S

OU(laquo OR raquo)

S A B= +

AB S


Transparent 215



A B S

0 0 1

0 1 0

1 0 0

1 1 1

AB S


A B S

0 0 0

0 1 1

1 0 1

1 1 0

AB S



Transparent 216




A1A2

An

A1A2

An

A1A2

An

A1A2

An

1 2 nS A A A= + + +L

1 2 nS A A A= + + +L



Transparent 217




Transparent 218




10

11

12

13

8

9

14

5

4

3

2

7

6

1A1

B1

S1

A2

B2

S2

A4

B4

S4

A3

B3

S3

VCC

GND

(suite)

Transparent 219




SN74LS02

SN74LS04

SN74LS08

SN74LS10

SN74LS32

SN74LS86A

Transparent 220



SN74LS86A


p

b1

b2

b3

b4

b1

b2

b3

b4

IMPARITEacute

PARITEacute5 volts

Transparent 221




A B S

bas bas bas

bas haut bas

haut bas bas

haut haut haut



Logique positive



AB S




AB S

Transparent 210




1 2 i i nS f A A A=1 2 1

0 0 0 0 10 0 0 1 10 0 1 0 0

1 1 1 1 1


L

L

L

M M M M M

L


Transparent 211








Transparent 212



A S

0 1

1 0

A S

INVERSEUR

S A=



Transparent 213



A B S

0 0 1

0 1 1

1 0 1

1 1 0

AB S


S AB=

A B S

0 0 0

0 1 0

1 0 0

1 1 1

AB S

ET(laquo AND raquo)

ou S A B AB= sdot

(suite)

Transparent 214



A B S

0 0 1

0 1 0

1 0 0

1 1 0

S A B= +

A B S

0 0 0

0 1 1

1 0 1

1 1 1

AB S

OU(laquo OR raquo)

S A B= +

AB S


Transparent 215



A B S

0 0 1

0 1 0

1 0 0

1 1 1

AB S


A B S

0 0 0

0 1 1

1 0 1

1 1 0

AB S



Transparent 216




A1A2

An

A1A2

An

A1A2

An

A1A2

An

1 2 nS A A A= + + +L

1 2 nS A A A= + + +L



Transparent 217




Transparent 218




10

11

12

13

8

9

14

5

4

3

2

7

6

1A1

B1

S1

A2

B2

S2

A4

B4

S4

A3

B3

S3

VCC

GND

(suite)

Transparent 219




SN74LS02

SN74LS04

SN74LS08

SN74LS10

SN74LS32

SN74LS86A

Transparent 220



SN74LS86A


p

b1

b2

b3

b4

b1

b2

b3

b4

IMPARITEacute

PARITEacute5 volts

Transparent 221




A B S

bas bas bas

bas haut bas

haut bas bas

haut haut haut



Logique positive



AB S




AB S

Transparent 211








Transparent 212



A S

0 1

1 0

A S

INVERSEUR

S A=



Transparent 213



A B S

0 0 1

0 1 1

1 0 1

1 1 0

AB S


S AB=

A B S

0 0 0

0 1 0

1 0 0

1 1 1

AB S

ET(laquo AND raquo)

ou S A B AB= sdot

(suite)

Transparent 214



A B S

0 0 1

0 1 0

1 0 0

1 1 0

S A B= +

A B S

0 0 0

0 1 1

1 0 1

1 1 1

AB S

OU(laquo OR raquo)

S A B= +

AB S


Transparent 215



A B S

0 0 1

0 1 0

1 0 0

1 1 1

AB S


A B S

0 0 0

0 1 1

1 0 1

1 1 0

AB S



Transparent 216




A1A2

An

A1A2

An

A1A2

An

A1A2

An

1 2 nS A A A= + + +L

1 2 nS A A A= + + +L



Transparent 217




Transparent 218




10

11

12

13

8

9

14

5

4

3

2

7

6

1A1

B1

S1

A2

B2

S2

A4

B4

S4

A3

B3

S3

VCC

GND

(suite)

Transparent 219




SN74LS02

SN74LS04

SN74LS08

SN74LS10

SN74LS32

SN74LS86A

Transparent 220



SN74LS86A


p

b1

b2

b3

b4

b1

b2

b3

b4

IMPARITEacute

PARITEacute5 volts

Transparent 221




A B S

bas bas bas

bas haut bas

haut bas bas

haut haut haut



Logique positive



AB S




AB S

Transparent 212



A S

0 1

1 0

A S

INVERSEUR

S A=



Transparent 213



A B S

0 0 1

0 1 1

1 0 1

1 1 0

AB S


S AB=

A B S

0 0 0

0 1 0

1 0 0

1 1 1

AB S

ET(laquo AND raquo)

ou S A B AB= sdot

(suite)

Transparent 214



A B S

0 0 1

0 1 0

1 0 0

1 1 0

S A B= +

A B S

0 0 0

0 1 1

1 0 1

1 1 1

AB S

OU(laquo OR raquo)

S A B= +

AB S


Transparent 215



A B S

0 0 1

0 1 0

1 0 0

1 1 1

AB S


A B S

0 0 0

0 1 1

1 0 1

1 1 0

AB S



Transparent 216




A1A2

An

A1A2

An

A1A2

An

A1A2

An

1 2 nS A A A= + + +L

1 2 nS A A A= + + +L



Transparent 217




Transparent 218




10

11

12

13

8

9

14

5

4

3

2

7

6

1A1

B1

S1

A2

B2

S2

A4

B4

S4

A3

B3

S3

VCC

GND

(suite)

Transparent 219




SN74LS02

SN74LS04

SN74LS08

SN74LS10

SN74LS32

SN74LS86A

Transparent 220



SN74LS86A


p

b1

b2

b3

b4

b1

b2

b3

b4

IMPARITEacute

PARITEacute5 volts

Transparent 221




A B S

bas bas bas

bas haut bas

haut bas bas

haut haut haut



Logique positive



AB S




AB S

Transparent 213



A B S

0 0 1

0 1 1

1 0 1

1 1 0

AB S


S AB=

A B S

0 0 0

0 1 0

1 0 0

1 1 1

AB S

ET(laquo AND raquo)

ou S A B AB= sdot

(suite)

Transparent 214



A B S

0 0 1

0 1 0

1 0 0

1 1 0

S A B= +

A B S

0 0 0

0 1 1

1 0 1

1 1 1

AB S

OU(laquo OR raquo)

S A B= +

AB S


Transparent 215



A B S

0 0 1

0 1 0

1 0 0

1 1 1

AB S


A B S

0 0 0

0 1 1

1 0 1

1 1 0

AB S



Transparent 216




A1A2

An

A1A2

An

A1A2

An

A1A2

An

1 2 nS A A A= + + +L

1 2 nS A A A= + + +L



Transparent 217




Transparent 218




10

11

12

13

8

9

14

5

4

3

2

7

6

1A1

B1

S1

A2

B2

S2

A4

B4

S4

A3

B3

S3

VCC

GND

(suite)

Transparent 219




SN74LS02

SN74LS04

SN74LS08

SN74LS10

SN74LS32

SN74LS86A

Transparent 220



SN74LS86A


p

b1

b2

b3

b4

b1

b2

b3

b4

IMPARITEacute

PARITEacute5 volts

Transparent 221




A B S

bas bas bas

bas haut bas

haut bas bas

haut haut haut



Logique positive



AB S




AB S

Transparent 214



A B S

0 0 1

0 1 0

1 0 0

1 1 0

S A B= +

A B S

0 0 0

0 1 1

1 0 1

1 1 1

AB S

OU(laquo OR raquo)

S A B= +

AB S


Transparent 215



A B S

0 0 1

0 1 0

1 0 0

1 1 1

AB S


A B S

0 0 0

0 1 1

1 0 1

1 1 0

AB S



Transparent 216




A1A2

An

A1A2

An

A1A2

An

A1A2

An

1 2 nS A A A= + + +L

1 2 nS A A A= + + +L



Transparent 217




Transparent 218




10

11

12

13

8

9

14

5

4

3

2

7

6

1A1

B1

S1

A2

B2

S2

A4

B4

S4

A3

B3

S3

VCC

GND

(suite)

Transparent 219




SN74LS02

SN74LS04

SN74LS08

SN74LS10

SN74LS32

SN74LS86A

Transparent 220



SN74LS86A


p

b1

b2

b3

b4

b1

b2

b3

b4

IMPARITEacute

PARITEacute5 volts

Transparent 221




A B S

bas bas bas

bas haut bas

haut bas bas

haut haut haut



Logique positive



AB S




AB S

Transparent 215



A B S

0 0 1

0 1 0

1 0 0

1 1 1

AB S


A B S

0 0 0

0 1 1

1 0 1

1 1 0

AB S



Transparent 216




A1A2

An

A1A2

An

A1A2

An

A1A2

An

1 2 nS A A A= + + +L

1 2 nS A A A= + + +L



Transparent 217




Transparent 218




10

11

12

13

8

9

14

5

4

3

2

7

6

1A1

B1

S1

A2

B2

S2

A4

B4

S4

A3

B3

S3

VCC

GND

(suite)

Transparent 219




SN74LS02

SN74LS04

SN74LS08

SN74LS10

SN74LS32

SN74LS86A

Transparent 220



SN74LS86A


p

b1

b2

b3

b4

b1

b2

b3

b4

IMPARITEacute

PARITEacute5 volts

Transparent 221




A B S

bas bas bas

bas haut bas

haut bas bas

haut haut haut



Logique positive



AB S




AB S

Transparent 216




A1A2

An

A1A2

An

A1A2

An

A1A2

An

1 2 nS A A A= + + +L

1 2 nS A A A= + + +L



Transparent 217




Transparent 218




10

11

12

13

8

9

14

5

4

3

2

7

6

1A1

B1

S1

A2

B2

S2

A4

B4

S4

A3

B3

S3

VCC

GND

(suite)

Transparent 219




SN74LS02

SN74LS04

SN74LS08

SN74LS10

SN74LS32

SN74LS86A

Transparent 220



SN74LS86A


p

b1

b2

b3

b4

b1

b2

b3

b4

IMPARITEacute

PARITEacute5 volts

Transparent 221




A B S

bas bas bas

bas haut bas

haut bas bas

haut haut haut



Logique positive



AB S




AB S

Transparent 217




Transparent 218




10

11

12

13

8

9

14

5

4

3

2

7

6

1A1

B1

S1

A2

B2

S2

A4

B4

S4

A3

B3

S3

VCC

GND

(suite)

Transparent 219




SN74LS02

SN74LS04

SN74LS08

SN74LS10

SN74LS32

SN74LS86A

Transparent 220



SN74LS86A


p

b1

b2

b3

b4

b1

b2

b3

b4

IMPARITEacute

PARITEacute5 volts

Transparent 221




A B S

bas bas bas

bas haut bas

haut bas bas

haut haut haut



Logique positive



AB S




AB S

Transparent 218




10

11

12

13

8

9

14

5

4

3

2

7

6

1A1

B1

S1

A2

B2

S2

A4

B4

S4

A3

B3

S3

VCC

GND

(suite)

Transparent 219




SN74LS02

SN74LS04

SN74LS08

SN74LS10

SN74LS32

SN74LS86A

Transparent 220



SN74LS86A


p

b1

b2

b3

b4

b1

b2

b3

b4

IMPARITEacute

PARITEacute5 volts

Transparent 221




A B S

bas bas bas

bas haut bas

haut bas bas

haut haut haut



Logique positive



AB S




AB S

Transparent 219




SN74LS02

SN74LS04

SN74LS08

SN74LS10

SN74LS32

SN74LS86A

Transparent 220



SN74LS86A


p

b1

b2

b3

b4

b1

b2

b3

b4

IMPARITEacute

PARITEacute5 volts

Transparent 221




A B S

bas bas bas

bas haut bas

haut bas bas

haut haut haut



Logique positive



AB S




AB S

Transparent 220



SN74LS86A


p

b1

b2

b3

b4

b1

b2

b3

b4

IMPARITEacute

PARITEacute5 volts

Transparent 221




A B S

bas bas bas

bas haut bas

haut bas bas

haut haut haut



Logique positive



AB S




AB S

Transparent 221




A B S

bas bas bas

bas haut bas

haut bas bas

haut haut haut



Logique positive



AB S




AB S

lectures recommandées : givone / sections 3.1 à 3 · transparent 2.3 2.1 – postulats et...

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