f. pépin - ensea · td bf533 f. pépin fichier de configuration programme de répétition...

TD BF533

F. Pépin

Fichier de configuration

Programme de répétition

Documentation technique du codec AD1836

Schéma de la carte ADSP-BF533 EZ-KIT Lite

L'objectif de ce TD est d'étudier le projet "C_Talkthrough_TDM" fourni par Analog Devices :

Pourquoi faut-il initialiser l'EBIU ?

Que permet de faire le bus SPI entre le microcontrôleur et le codec ?

Comment la fin du transfert SPI est-elle gérée ?

Quelle est la fréquence d'échantillonnage du signal analogique ?

Quelle est la fréquence d'exécution du programme ISR.c ?

Expliquer le rôle de la ligne dans le fichier ISR.c :EX_INTERRUPT_HANDLER(Sport0_RX_ISR)

Quel est la fonction de l'instruction :*pDMA1_IRQ_STATUS = 0x0001;

Expliquer les lignes :iChannel0LeftIn = iRxBuffer1[INTERNAL_ADC_L0];iChannel0RightIn = iRxBuffer1[INTERNAL_ADC_R0];

A quel instant dans le programme la répétition des échantillons numériques est-elle faite ?

Suivre l'échantillon, à partir du connecteur d'entrée jusqu'au connecteur de sortie.

Implanter un filtre numérique.

Fichier de configuration ADSP-BF533_ASM.ldf :

ARCHITECTURE(ADSP-BF533)

SEARCH_DIR( $ADI_DSP\Blackfin\lib )

$OBJECTS = $COMMAND_LINE_OBJECTS;$LIBRARIES = $COMMAND_LINE_OBJECTS;

MEMORY{ /* Instruction SRAM, 48K */

PROGRAM { TYPE(RAM) START(0xFFA00000) END(0xFFA04FFF) WIDTH(8) }/* Data Bank A, 16K */DATA_A { TYPE(RAM) START(0xFF800000) END(0xFF807FFF) WIDTH(8) }/* Data Bank B, 16K */DATA_B { TYPE(RAM) START(0xFF900000) END(0xFF907FFF) WIDTH(8) }/* Scratch SRAM, 4K */SCRATCH { TYPE(RAM) START(0xFFB00000) END(0xFFB00FFF) WIDTH(8) }/* SDRAM memory, 4K */SDRAM_MEM { TYPE(RAM) START(0x00000000) END(0x07FFFFFF) WIDTH(8) }

}

PROCESSOR p0{

OUTPUT( $COMMAND_LINE_OUTPUT_FILE )

SECTIONS{program

{INPUT_SECTION_ALIGN(4)INPUT_SECTIONS( $OBJECTS(program) $LIBRARIES(program))INPUT_SECTIONS( $OBJECTS(L1_code) $LIBRARIES(L1_code))

} >PROGRAM

data_a{

INPUT_SECTION_ALIGN(4)INPUT_SECTIONS($OBJECTS(data_a) $LIBRARIES(data_a))INPUT_SECTIONS($OBJECTS(L1_data_a) $LIBRARIES(L1_data_a))

} >DATA_A

data_b{

INPUT_SECTION_ALIGN(4)INPUT_SECTIONS($OBJECTS(data_b) $LIBRARIES(data_b))INPUT_SECTIONS($OBJECTS(L1_data_b) $LIBRARIES(L1_data_b))

} >DATA_B

scratch{

INPUT_SECTION_ALIGN(4)INPUT_SECTIONS($OBJECTS(scratchpad) $LIBRARIES(scratchpad))

} >SCRATCH

}}

/* Fichier main.c */

//----------------------------------------------------------------------------//// //// Name: Talkthrough for the ADSP-BF533 EZ-KIT Lite //// ////----------------------------------------------------------------------------//// //// (C) Copyright 2006 - Analog Devices, Inc. All rights reserved. //// //// Project Name: BF533 C Talkthrough TDM //// //// Date Modified: 04/03/03 Rev 1.0 //// //// Software: VisualDSP++4.5 //// //// Hardware: ADSP-BF533 EZ-KIT Board //// //// Connections: Disconnect RSCLK0 and TSCLK0 (Turn SW9 pin 6 OFF) //// Disconnect RFS0 and TFS0 (Turn SW9 pin 5 OFF) //// Connect an input source (such as a radio) to the //// Audio input jack and an output source (such as //// headphones) to the Audio output jack //// //// Purpose: This program sets up the SPI port on the ADSP-BF533 to//// configure the AD1836 codec. The SPI port is disabled //// after initialization. The data to/from the codec are //// transfered over SPORT0 in TDM mode //// ////----------------------------------------------------------------------------//

#include "Talkthrough.h"#include "sysreg.h"#include "ccblkfn.h"

//----------------------------------------------------------------------------//// Variables //// //// Description: The variables iChannelxLeftIn and iChannelxRightIn contain //// the data coming from the codec AD1836. The (processed) //// playback data are written into the variables //// iChannelxLeftOut and iChannelxRightOut respectively, which //// are then sent back to the codec in the SPORT0 ISR. //// The values in the array iCodec1836TxRegs can be modified to //// set up the codec in different configurations according to //// the AD1885 data sheet. ////----------------------------------------------------------------------------//

// left input data from ad1836int iChannel0LeftIn, iChannel1LeftIn;

// right input data from ad1836int iChannel0RightIn, iChannel1RightIn;

// left ouput data for ad1836int iChannel0LeftOut, iChannel1LeftOut;

// right ouput data for ad1836int iChannel0RightOut, iChannel1RightOut;

// array for registers to configure the ad1836// names are defined in "Talkthrough.h"volatile short sCodec1836TxRegs[CODEC_1836_REGS_LENGTH] ={

DAC_CONTROL_1 | 0x000,DAC_CONTROL_2 | 0x000,DAC_VOLUME_0 | 0x3ff,DAC_VOLUME_1 | 0x3ff,DAC_VOLUME_2 | 0x3ff,DAC_VOLUME_3 | 0x3ff,DAC_VOLUME_4 | 0x3ff,DAC_VOLUME_5 | 0x3ff,ADC_CONTROL_1 | 0x000,ADC_CONTROL_2 | 0x180,ADC_CONTROL_3 | 0x000

};// SPORT0 DMA transmit buffervolatile int iTxBuffer1[8];// SPORT0 DMA receive buffervolatile int iRxBuffer1[8];

//-------------------------------------------------------------------------- //// Function: main //// //// Description: After calling a few initalization routines, main() just //// waits in a loop forever. The code to process the incoming //// data can be placed in the function Process_Data() in the //// file "Process_Data.c". ////---------------------------------------------------------------------------//void main(void){

sysreg_write(reg_SYSCFG, 0x32); //Initialize System Configuration RegisterInit_EBIU();Init_Flash();Init1836();Init_Sport0();Init_DMA();Init_Sport_Interrupts();Enable_DMA_Sport0();

while(1);}

/* Fichier initialisation.c */

#include "Talkthrough.h"

//----------------------------------------------------------------------------//// Function: Init_EBIU //// //// Description: This function initializes and enables asynchronous memory //// banks in External Bus Interface Unit so that Flash A can be //// accessed. ////----------------------------------------------------------------------------//void Init_EBIU(void){

*pEBIU_AMBCTL0 = 0x7bb07bb0;*pEBIU_AMBCTL1 = 0x7bb07bb0;*pEBIU_AMGCTL = 0x000f;

}

//----------------------------------------------------------------------------//// Function: Init_Flash //// //// Description: This function initializes pin direction of Port A in Flash A//// to output. The AD1836_RESET on the ADSP-BF533 EZ-KIT board //// is connected to Port A. ////----------------------------------------------------------------------------//void Init_Flash(void){

*pFlashA_PortA_Dir = 0x1;}

//----------------------------------------------------------------------------//// Function: Init1836() //// //// Description: This function sets up the SPI port to configure the AD1836. //// The content of the array sCodec1836TxRegs is sent to the //// codec. ////----------------------------------------------------------------------------//void Init1836(void){

int i;int j;static unsigned char ucActive_LED = 0x01;

// write to Port A to reset AD1836*pFlashA_PortA_Data = 0x00;

// write to Port A to enable AD1836*pFlashA_PortA_Data = ucActive_LED;

// wait to recover from resetfor (i=0; i<0xf000; i++) asm("nop;");

// Enable PF4*pSPI_FLG = FLS4;

// Set baud rate SCK = HCLK/(2*SPIBAUD) SCK = 2MHz*pSPI_BAUD = 16;

// configure spi port// SPI DMA write, 16-bit data, MSB first, SPI Master*pSPI_CTL = TIMOD_DMA_TX | SIZE | MSTR;

// Set up DMA5 to transmit// Map DMA5 to SPI*pDMA5_PERIPHERAL_MAP = 0x5000;

// Configure DMA5// 16-bit transfers*pDMA5_CONFIG = WDSIZE_16;// Start address of data buffer*pDMA5_START_ADDR = (void *)sCodec1836TxRegs;// DMA inner loop count*pDMA5_X_COUNT = CODEC_1836_REGS_LENGTH;// Inner loop address increment*pDMA5_X_MODIFY = 2;

// enable DMAs*pDMA5_CONFIG = (*pDMA5_CONFIG | DMAEN);// enable spi*pSPI_CTL = (*pSPI_CTL | SPE);

// wait until dma transfers for spi are finishedfor (j=0; j<0xaff0; j++) asm("nop;");

// disable spi*pSPI_CTL = 0x0000;

}

//----------------------------------------------------------------------------//// Function: Init_Sport0 //// //// Description: Configure Sport0 for TDM mode, to transmit/receive data //// to/from the AD1836. Configure Sport for external clocks and //// frame syncs. ////----------------------------------------------------------------------------//void Init_Sport0(void){

// Sport0 receive configuration// External CLK, External Frame sync, MSB first// 32-bit data*pSPORT0_RCR1 = RFSR;*pSPORT0_RCR2 = SLEN_32;

// Sport0 transmit configuration// External CLK, External Frame sync, MSB first// 24-bit data*pSPORT0_TCR1 = TFSR;*pSPORT0_TCR2 = SLEN_32;

// Enable MCM 8 transmit & receive channels*pSPORT0_MTCS0 = 0x000000FF;*pSPORT0_MRCS0 = 0x000000FF;

// Set MCM configuration register and enable MCM mode*pSPORT0_MCMC1 = 0x0000;*pSPORT0_MCMC2 = 0x101c;

}

//----------------------------------------------------------------------------//// Function: Init_DMA //// //// Description: Initialize DMA1 in autobuffer mode to receive and DMA2 in //// autobuffer mode to transmit ////----------------------------------------------------------------------------//

void Init_DMA(void){

// Set up DMA1 to receive// Map DMA1 to Sport0 RX*pDMA1_PERIPHERAL_MAP = 0x1000;

// Configure DMA1// 32-bit transfers, Interrupt on completion, Autobuffer mode*pDMA1_CONFIG = WNR | WDSIZE_32 | DI_EN | FLOW_1;// Start address of data buffer*pDMA1_START_ADDR = (void *)iRxBuffer1;// DMA inner loop count*pDMA1_X_COUNT = 8;// Inner loop address increment*pDMA1_X_MODIFY = 4;

// Set up DMA2 to transmit// Map DMA2 to Sport0 TX*pDMA2_PERIPHERAL_MAP = 0x2000;

// Configure DMA2// 32-bit transfers, Autobuffer mode*pDMA2_CONFIG = WDSIZE_32 | FLOW_1;// Start address of data buffer*pDMA2_START_ADDR = (void *)iTxBuffer1;// DMA inner loop count*pDMA2_X_COUNT = 8;// Inner loop address increment*pDMA2_X_MODIFY = 4;

}

//----------------------------------------------------------------------------//// Function: Init_Interrupts //// //// Description: Initialize Interrupt for Sport0 RX ////----------------------------------------------------------------------------//void Init_Sport_Interrupts(void){

// Set Sport0 RX (DMA1) interrupt priority to 2 = IVG9*pSIC_IAR0 = 0xffffffff;*pSIC_IAR1 = 0xffffff2f;*pSIC_IAR2 = 0xffffffff;

// assign ISRs to interrupt vectors// Sport0 RX ISR -> IVG 9register_handler(ik_ivg9, Sport0_RX_ISR);

// enable Sport0 RX interrupt*pSIC_IMASK = 0x00000200;ssync();

}

//----------------------------------------------------------------------------//// Function: Enable_DMA_Sport //// //// Description: Enable DMA1, DMA2, Sport0 TX and Sport0 RX ////----------------------------------------------------------------------------//void Enable_DMA_Sport0(void){

// enable DMAs*pDMA2_CONFIG = (*pDMA2_CONFIG | DMAEN);

*pDMA1_CONFIG = (*pDMA1_CONFIG | DMAEN);

// enable Sport0 TX and RX*pSPORT0_TCR1 = (*pSPORT0_TCR1 | TSPEN);*pSPORT0_RCR1 = (*pSPORT0_RCR1 | RSPEN);

}

/* Fichier ISR.c */


//----------------------------------------------------------------------------//// Function: Sport0_RX_ISR //// //// Description: This ISR is executed after a complete frame of input data //// has been received. The new samples are stored in //// iChannel0LeftIn, iChannel0RightIn, iChannel1LeftIn and //// iChannel1RightIn respectively. Then the function //// Process_Data() is called in which user code can be executed.//// After that the processed values are copied from the //// variables iChannel0LeftOut, iChannel0RightOut, //// iChannel1LeftOut and iChannel1RightOut into the dma //// transmit buffer. ////----------------------------------------------------------------------------//EX_INTERRUPT_HANDLER(Sport0_RX_ISR){

// confirm interrupt handling*pDMA1_IRQ_STATUS = 0x0001;

// copy input data from dma input buffer into variablesiChannel0LeftIn = iRxBuffer1[INTERNAL_ADC_L0];iChannel0RightIn = iRxBuffer1[INTERNAL_ADC_R0];iChannel1LeftIn = iRxBuffer1[INTERNAL_ADC_L1];iChannel1RightIn = iRxBuffer1[INTERNAL_ADC_R1];

// call function that contains user codeProcess_Data();

// copy processed data from variables into dma output bufferiTxBuffer1[INTERNAL_DAC_L0] = iChannel0LeftOut;iTxBuffer1[INTERNAL_DAC_R0] = iChannel0RightOut;iTxBuffer1[INTERNAL_DAC_L1] = iChannel1LeftOut;iTxBuffer1[INTERNAL_DAC_L2] = iChannel1LeftOut;iTxBuffer1[INTERNAL_DAC_R1] = iChannel1RightOut;iTxBuffer1[INTERNAL_DAC_R2] = iChannel1RightOut;

}

/* Fichier process_data.c */


//----------------------------------------------------------------------------//// Function: Process_Data() //// //// Description: This function is called from inside the SPORT0 ISR every //// time a complete audio frame has been received. The new //// input samples can be found in the variables iChannel0LeftIn,//// iChannel0RightIn, iChannel1LeftIn and iChannel1RightIn //// respectively. The processed data should be stored in //// iChannel0LeftOut, iChannel0RightOut, iChannel1LeftOut, //// iChannel1RightOut, iChannel2LeftOut and iChannel2RightOut //// respectively. ////----------------------------------------------------------------------------//void Process_Data(void){

iChannel0LeftOut = iChannel0LeftIn;iChannel0RightOut = iChannel0RightIn;iChannel1LeftOut = iChannel1LeftIn;iChannel1RightOut = iChannel1RightIn;

}

/* Fichier talkthrough.h */

#ifndef __Talkthrough_DEFINED#define __Talkthrough_DEFINED

//----------------------------------------------------------------------------//// Header files ////----------------------------------------------------------------------------//#include <sys\exception.h>#include <cdefBF533.h>#include <ccblkfn.h>#include <sysreg.h>

//----------------------------------------------------------------------------//// Symbolic constants ////----------------------------------------------------------------------------//// addresses for Port B in Flash A#define pFlashA_PortA_Dir (volatile unsigned char *)0x20270006#define pFlashA_PortA_Data (volatile unsigned char *)0x20270004

// names for codec registers, used for iCodec1836TxRegs[]#define DAC_CONTROL_1 0x0000#define DAC_CONTROL_2 0x1000#define DAC_VOLUME_0 0x2000#define DAC_VOLUME_1 0x3000#define DAC_VOLUME_2 0x4000#define DAC_VOLUME_3 0x5000#define DAC_VOLUME_4 0x6000#define DAC_VOLUME_5 0x7000#define ADC_0_PEAK_LEVEL 0x8000#define ADC_1_PEAK_LEVEL 0x9000#define ADC_2_PEAK_LEVEL 0xA000#define ADC_3_PEAK_LEVEL 0xB000#define ADC_CONTROL_1 0xC000#define ADC_CONTROL_2 0xD000#define ADC_CONTROL_3 0xE000

// names for slots in ad1836 audio frame#define INTERNAL_ADC_L0 0#define INTERNAL_ADC_L1 1#define INTERNAL_ADC_R0 4#define INTERNAL_ADC_R1 5#define INTERNAL_DAC_L0 0#define INTERNAL_DAC_L1 1#define INTERNAL_DAC_L2 2#define INTERNAL_DAC_R0 4#define INTERNAL_DAC_R1 5#define INTERNAL_DAC_R2 6

// size of array iCodec1836TxRegs and iCodec1836RxRegs#define CODEC_1836_REGS_LENGTH 11

// SPI transfer mode#define TIMOD_DMA_TX 0x0003

// SPORT0 word length#define SLEN_32 0x001f

// DMA flow mode#define FLOW_1 0x1000

//----------------------------------------------------------------------------//

// Global variables ////----------------------------------------------------------------------------//extern int iChannel0LeftIn;extern int iChannel0RightIn;extern int iChannel0LeftOut;extern int iChannel0RightOut;extern int iChannel1LeftIn;extern int iChannel1RightIn;extern int iChannel1LeftOut;extern int iChannel1RightOut;extern volatile short sCodec1836TxRegs[];extern volatile int iRxBuffer1[];extern volatile int iTxBuffer1[];

//----------------------------------------------------------------------------//// Prototypes ////----------------------------------------------------------------------------//// in file Initialisation.cvoid Init_EBIU(void);void Init_Flash(void);void Init1836(void);void Init_Sport0(void);void Init_DMA(void);void Init_Sport_Interrupts(void);void Enable_DMA_Sport(void);void Enable_DMA_Sport0(void);

// in file Process_data.cvoid Process_Data(void);

// in file ISRs.cEX_INTERRUPT_HANDLER(Sport0_RX_ISR);

#endif //__Talkthrough_DEFINED

/* Fichier C_Talkthrough_TDM_basiccrt.s */

/* MANAGED-BY-SYSTEM-BUILDER */

/*** C_Talkthrough_TDM_basiccrt.s generated on Jul 23, 2012 at 14:04:22.**** Copyright (C) 2000-2006 Analog Devices Inc., All Rights Reserved.** This contains Analog Devices Background IP and Development IP as** defined in the ADI/Intel Collaboration Agreement.**** This file is generated automatically based upon the options selected** in the Startup Code Wizard. Changes to the startup configuration** should be made by changing the appropriate options rather than** editing this file. Additional user code to be executed before calling** main can be inserted between the labels .start_of_user_code1 and** .end_of_user_code1 or .start_of_user_code2 and .end_of_user_code2.** This code is preserved if the CRT is re-generated.**** Configuration:-** processor: ADSP-BF533** si_revision: automatic** cplb_init: false** mem_init: false** device_init: false** init_regs: false** zero_return_regs: false** use_profiling: false** set_clock_and_power: true** platform: bf533_600mhz_ezkit** optimize_clocks_for_speed: true***/

/////////////////////////////////////////////////////////////////// blackfin-edinburgh-core#include <sys/platform.h>#include <sys/anomaly_macros_rtl.h>

/////////////////////////////////////////////////////////////////// standard#define IVBh (EVT0 >> 16)#define IVBl (EVT0 & 0xFFFF)#define UNASSIGNED_VAL 0x8181#define INTERRUPT_BITS 0x400 // just IVG15#define SYSCFG_VALUE 0x30

.section/DOUBLEANY program;

.file_attr requiredForROMBoot;

.align 2;

start:

/////////////////////////////////////////////////////////////////// blackfin-edinburgh-core#if WA_05000109

// Avoid Anomaly 05-00-0109R1 = SYSCFG_VALUE;SYSCFG = R1;

#endif

/////////////////////////////////////////////////////////////////

// standard#if WA_05000229

// Avoid Anomaly 05-00-0229: DMA5_CONFIG and SPI_CTL not cleared on reset.R1 = 0x400;

#if defined(__ADSPBF538__) || defined(__ADSPBF539__)P0.L = SPI0_CTL & 0xFFFF;P0.H = SPI0_CTL >> 16;W[P0] = R1.L;

#elseP0.L = SPI_CTL & 0xFFFF;P0.H = SPI_CTL >> 16;W[P0] = R1.L;

#endifP0.L = DMA5_CONFIG & 0xFFFF;P0.H = DMA5_CONFIG >> 16;R1 = 0;W[P0] = R1.L;

#endif// Zap loop counters to zero, to make sure that// hw loops are disabled - it could be really baffling// if the counters and bottom regs are set, and we happen// to run into them.R7 = 0;LC0 = R7;LC1 = R7;

// Clear the DAG Length regs too, so that it's safe to// use I-regs without them wrapping around.L0 = R7;L1 = R7;L2 = R7;L3 = R7;

// Zero ITEST_COMMAND and DTEST_COMMAND// (in case they have crud in them and// does a write somewhere when we enable cache)I0.L = (ITEST_COMMAND & 0xFFFF);I0.H = (ITEST_COMMAND >> 16);I1.L = (DTEST_COMMAND & 0xFFFF);I1.H = (DTEST_COMMAND >> 16);[I0] = R7;[I1] = R7;CSYNC;

// Initialise the Event Vector table.P0.H = IVBh;P0.L = IVBl;

// Install __unknown_exception_occurred in EVT so that// there is defined behaviour.P0 += 2*4; // Skip Emulation and ResetP1 = 13;R1.L = __unknown_exception_occurred;R1.H = __unknown_exception_occurred;LSETUP (.ivt,.ivt) LC0 = P1;

.ivt: [P0++] = R1;

// Set IVG15's handler to be the start of the mode-change// code. Then, before we return from the Reset back to user// mode, we'll raise IVG15. This will mean we stay in supervisor// mode, and continue from the mode-change point, but at a// much lower priority.

P1.H = supervisor_mode;P1.L = supervisor_mode;[P0] = P1;

/////////////////////////////////////////////////////////////////// standard

// Initialise the stack.// Note: this points just past the end of the section.// First write should be with [--SP].SP.L=ldf_stack_end;SP.H=ldf_stack_end;usp = sp;

// We're still in supervisor mode at the moment, so the FP// needs to point to the supervisor stack.FP = SP;

// And make space for incoming "parameters" for functions// we call from here:SP += -12;

R0 = INTERRUPT_BITS;R0 <<= 5; // Bits 0-4 not settable.CALL.X __install_default_handlers;

R1 = SYSCFG;R4 = R0; // Save modified list for laterBITSET(R1,1);SYSCFG = R1; // Enable the cycle counter

/////////////////////////////////////////////////////////////////// blackfin-edinburgh-core#if WA_05000137

// Avoid Anomaly 02-00-0137// Set the port preferences of DAG0 and DAG1 to be// different; this gives better performance when// performing daul-dag operations on SDRAM.P0.L = DMEM_CONTROL & 0xFFFF;P0.H = DMEM_CONTROL >> 16;R0 = [P0];BITSET(R0, 12);BITCLR(R0, 13);[P0] = R0;CSYNC;

#endif

/*$VDSG<insert-code-early-startup> */.start_of_user_code1:

// Insert additional code to be executed before main here.// This code is preserved if the CRT is re-generated.

.end_of_user_code1:/*$VDSG<insert-code-early-startup> */

/////////////////////////////////////////////////////////////////// clock-and-power-set#include <services/services.h>

// Call initialisation functions for System// Services libarary clock and power managementR0.L = _adi_crt_ebiu_ezkit_config;R0.H = _adi_crt_ebiu_ezkit_config;R1 = 0; //AdjustRefreshRate=0

CALL.X _adi_ebiu_Init;R0.L = _adi_crt_pwr_ezkit_config;R0.H = _adi_crt_pwr_ezkit_config;CALL.X _adi_pwr_Init;

.extern _adi_ebiu_Init;

.type _adi_ebiu_Init,STT_FUNC;

.extern _adi_pwr_Init;

.type _adi_pwr_Init,STT_FUNC;

.section/DOUBLEANY data1;

.align 4;_adi_crt_ebiu_ezkit_config:

.global _adi_crt_ebiu_ezkit_config;.type _adi_crt_ebiu_ezkit_config,STT_OBJECT;

/////////////////////////////////////////////////////////////////// bf533-ezkit

.byte4 = ADI_EBIU_CMD_SET_EZKIT, ADI_EBIU_EZKIT_BF533,

/////////////////////////////////////////////////////////////////// clock-and-power-set

ADI_EBIU_CMD_END, 0 /*padding*/;._adi_crt_ebiu_ezkit_config.end:

_adi_crt_pwr_ezkit_config:.global _adi_crt_pwr_ezkit_config;.type _adi_crt_pwr_ezkit_config,STT_OBJECT;

/////////////////////////////////////////////////////////////////// bf533-600mhz-ezkit

.byte4 = ADI_PWR_CMD_SET_EZKIT, ADI_PWR_EZKIT_BF533_600MHZ;

/////////////////////////////////////////////////////////////////// clock-and-power-set

.byte4 = ADI_PWR_CMD_END, 0 /*padding*/;._adi_crt_pwr_ezkit_config.end:

.section/DOUBLEANY program;

.align 2;

/////////////////////////////////////////////////////////////////// optimize-clocks-for-speed

// Optimize clock frequency for processor speedR0 = 0;R1 = R0;R2 = ADI_PWR_DF_NONE;CALL.X _adi_pwr_SetFreq;

.extern _adi_pwr_SetFreq;

.type _adi_pwr_SetFreq,STT_FUNC;

/////////////////////////////////////////////////////////////////// standard

// Enable interruptsSTI R4; // Using the mask from default handlersRAISE 15;

// Move the processor into user mode.P0.L=still_interrupt_in_ipend;P0.H=still_interrupt_in_ipend;RETI=P0;NOP; // Purely to prevent a stall warning

still_interrupt_in_ipend:// execute RTI until we've `finished` servicing all// interrupts of priority higher than IVG15. Normally one// would expect to only have the reset interrupt in IPEND// being serviced, but occasionally when debugging this may// not be the case - if restart is hit when servicing an// interrupt.//// When we clear all bits from IPEND, we'll enter user mode,// then we'll automatically jump to supervisor_mode to start// servicing IVG15 (which we will 'service' for the whole// program, so that the program is in supervisor mode.// Need to do this to 'finish' servicing the reset interupt.RTI;

supervisor_mode:[--SP] = RETI; // re-enables the interrupt systemR0.L = UNASSIGNED_VAL;R0.H = UNASSIGNED_VAL;

// Push a RETS and Old FP onto the stack, for sanity.[--SP]=R0;[--SP]=R0;// Make sure the FP is sensible.FP = SP;// And leave space for incoming "parameters"SP += -12;

/*$VDSG<insert-code-before-device-initialization> */.start_of_user_code2:

// Insert additional code to be executed before device initialization here.// This code is preserved if the CRT is re-generated.

.end_of_user_code2:/*$VDSG<insert-code-before-device-initialization> */

/////////////////////////////////////////////////////////////////// cplusplus

CALL.X ___ctorloop; // run global scope C++ constructors.extern ___ctorloop;.type ___ctorloop,STT_FUNC;

/*$VDSG<insert-code-before-main-entry> */.start_of_user_code3:

// Insert additional code to be executed before main here.// This code is preserved if the CRT is re-generated.

.end_of_user_code3:/*$VDSG<insert-code-before-main-entry> */

/////////////////////////////////////////////////////////////////// get-args

// Read command-line arguments.CALL.X __getargv;r1.l=__Argv;r1.h=__Argv;

.extern __getargv;

.type __getargv,STT_FUNC;

.extern __Argv;

.type __Argv,STT_OBJECT;

/////////////////////////////////////////////////////////////////// standard

// At long last, call the application program.CALL.X _main;

/////////////////////////////////////////////////////////////////// call-exit

CALL.X _exit; // passing in main's return value.extern _exit;.type _exit,STT_FUNC;

/////////////////////////////////////////////////////////////////// standard.start.end: // To keep the linker happy.

.global start;

.type start,STT_FUNC;

.global .start.end;

.type .start.end,STT_FUNC;

.extern _main;

.type _main,STT_FUNC;

.extern ldf_stack_end;

.extern __unknown_exception_occurred;

.type __unknown_exception_occurred,STT_FUNC;

.extern __install_default_handlers;

.type __install_default_handlers,STT_FUNC;

/////////////////////////////////////////////////////////////////// no-device-initialization

// If File IO support isn't provided, then// we provide dummy versions of the device-handling// functions, so that the exception handlers don't rely// on the file IO library.section/DOUBLEANY program;.align 2;

_dev_open:_dev_close:_dev_write:_dev_read:_dev_seek:_dev_dup:

R0 = -1;RTS;

._dev_open.end:

._dev_close.end:

._dev_write.end:

._dev_read.end:

._dev_seek.end:

._dev_dup.end:

.global _dev_open;

.type _dev_open,STT_FUNC;

.global _dev_close;

.type _dev_close,STT_FUNC;

.global _dev_write;

.type _dev_write,STT_FUNC;

.global _dev_read;

.type _dev_read,STT_FUNC;

.global _dev_seek;

.type _dev_seek,STT_FUNC;

.global _dev_dup;

.type _dev_dup,STT_FUNC;

/////////////////////////////////////////////////////////////////// cplusplus.section/DOUBLEANY ctor;

.align 4;___ctor_table:

.byte4=0;.global ___ctor_table;.type ___ctor_table,STT_OBJECT;.section/DOUBLEANY .gdt;

.align 4;___eh_gdt:.global ___eh_gdt;

.byte4=0;.type ___eh_gdt,STT_OBJECT;.section/DOUBLEANY .frt;

.align 4;___eh_frt:.global ___eh_frt;

.byte4=0;.type ___eh_frt,STT_OBJECT;

Fichier cdefBF533.h :

/************************************************************************** cdefBF533.h** (c) Copyright 2002-2003 Analog Devices, Inc. All rights reserved.*************************************************************************/

#ifndef _CDEFBF533_H#define _CDEFBF533_H

#include <cdefBF532.h>

#endif /* _CDEFBF533_H */

Une partie du fichier cdefBF532.h :

/************************************************************************** cdefBF532.h** (c) Copyright 2001-2006 Analog Devices, Inc. All rights reserved.*************************************************************************/

#ifndef _CDEF_BF532_H#define _CDEF_BF532_H

#if !defined(__ADSPLPBLACKFIN__)#warning cdefBF532.h should only be included for 532 compatible chips.#endif/* include all Core registers and bit definitions */#include <defBF532.h>

/* include core specific register pointer definitions */#include <cdef_LPBlackfin.h>

/* Clock and System Control (0xFFC0 0400-0xFFC0 07FF) */#define pPLL_CTL ((volatile unsigned short *)PLL_CTL)#define pPLL_STAT ((volatile unsigned short *)PLL_STAT)#define pPLL_LOCKCNT ((volatile unsigned short *)PLL_LOCKCNT)#define pSWRST ((volatile unsigned short *)SWRST)#define pSYSCR ((volatile unsigned short *)SYSCR)#define pPLL_DIV ((volatile unsigned short *)PLL_DIV)#define pVR_CTL ((volatile unsigned short *)VR_CTL)

/* System Interrupt Controller (0xFFC0 0C00-0xFFC0 0FFF) */#define pSIC_IAR0 ((volatile unsigned long *)SIC_IAR0)#define pSIC_IAR1 ((volatile unsigned long *)SIC_IAR1)#define pSIC_IAR2 ((volatile unsigned long *)SIC_IAR2)#define pSIC_IMASK ((volatile unsigned long *)SIC_IMASK)#define pSIC_ISR ((volatile unsigned long *)SIC_ISR)#define pSIC_IWR ((volatile unsigned long *)SIC_IWR)

/* Watchdog Timer (0xFFC0 1000-0xFFC0 13FF) */#define pWDOG_CTL ((volatile unsigned short *)WDOG_CTL)#define pWDOG_CNT ((volatile unsigned long *)WDOG_CNT)#define pWDOG_STAT ((volatile unsigned long *)WDOG_STAT)

/* Real Time Clock (0xFFC0 1400-0xFFC0 17FF) */#define pRTC_STAT ((volatile unsigned long *)RTC_STAT)#define pRTC_ICTL ((volatile unsigned short *)RTC_ICTL)#define pRTC_ISTAT ((volatile unsigned short *)RTC_ISTAT)#define pRTC_SWCNT ((volatile unsigned short *)RTC_SWCNT)#define pRTC_ALARM ((volatile unsigned long *)RTC_ALARM)#define pRTC_FAST ((volatile unsigned short *)RTC_FAST)#define pRTC_PREN ((volatile unsigned short *)RTC_PREN)

/* General Purpose IO (0xFFC0 2400-0xFFC0 27FF) */#define pFIO_DIR ((volatile unsigned short *)FIO_DIR)#define pFIO_FLAG_C ((volatile unsigned short *)FIO_FLAG_C)#define pFIO_FLAG_S ((volatile unsigned short *)FIO_FLAG_S)#define pFIO_MASKA_C ((volatile unsigned short *)FIO_MASKA_C)#define pFIO_MASKA_S ((volatile unsigned short *)FIO_MASKA_S)#define pFIO_MASKB_C ((volatile unsigned short *)FIO_MASKB_C)#define pFIO_MASKB_S ((volatile unsigned short *)FIO_MASKB_S)#define pFIO_POLAR ((volatile unsigned short *)FIO_POLAR)#define pFIO_EDGE ((volatile unsigned short *)FIO_EDGE)#define pFIO_BOTH ((volatile unsigned short *)FIO_BOTH)#define pFIO_INEN ((volatile unsigned short *)FIO_INEN)#define pFIO_FLAG_D ((volatile unsigned short *)FIO_FLAG_D)#define pFIO_FLAG_T ((volatile unsigned short *)FIO_FLAG_T)#define pFIO_MASKA_D ((volatile unsigned short *)FIO_MASKA_D)#define pFIO_MASKA_T ((volatile unsigned short *)FIO_MASKA_T)#define pFIO_MASKB_D ((volatile unsigned short *)FIO_MASKB_D)#define pFIO_MASKB_T ((volatile unsigned short *)FIO_MASKB_T)

/* DMA Traffic controls */#define pDMA_TC_PER ((volatile unsigned short *)DMA_TC_PER)#define pDMA_TC_CNT ((volatile unsigned short *)DMA_TC_CNT)

/* Alternate deprecated register names (below) provided for backwards codecompatibility */#define pDMA_TCPER ((volatile unsigned short *)DMA_TCPER)#define pDMA_TCCNT ((volatile unsigned short *)DMA_TCCNT)

/* DMA Controller */#define pDMA0_CONFIG ((volatile unsigned short *)DMA0_CONFIG)#define pDMA0_NEXT_DESC_PTR (_PTR_TO_VOL_VOID_PTR DMA0_NEXT_DESC_PTR)#define pDMA0_START_ADDR (_PTR_TO_VOL_VOID_PTR DMA0_START_ADDR)#define pDMA0_X_COUNT ((volatile unsigned short *)DMA0_X_COUNT)#define pDMA0_Y_COUNT ((volatile unsigned short *)DMA0_Y_COUNT)#define pDMA0_X_MODIFY ((volatile signed short *)DMA0_X_MODIFY)#define pDMA0_Y_MODIFY ((volatile signed short *)DMA0_Y_MODIFY)#define pDMA0_CURR_DESC_PTR (_PTR_TO_VOL_VOID_PTR DMA0_CURR_DESC_PTR)#define pDMA0_CURR_ADDR (_PTR_TO_VOL_VOILD_PTR DMA0_CURR_ADDR)#define pDMA0_CURR_X_COUNT ((volatile unsigned short *)DMA0_CURR_X_COUNT)#define pDMA0_CURR_Y_COUNT ((volatile unsigned short *)DMA0_CURR_Y_COUNT)#define pDMA0_IRQ_STATUS ((volatile unsigned short *)DMA0_IRQ_STATUS)#define pDMA0_PERIPHERAL_MAP ((volatile unsigned short *)DMA0_PERIPHERAL_MAP)

#define pDMA1_CONFIG ((volatile unsigned short *)DMA1_CONFIG)#define pDMA1_NEXT_DESC_PTR ((volatile void **)DMA1_NEXT_DESC_PTR)#define pDMA1_START_ADDR (_PTR_TO_VOL_VOID_PTR DMA1_START_ADDR)#define pDMA1_X_COUNT ((volatile unsigned short *)DMA1_X_COUNT)#define pDMA1_Y_COUNT ((volatile unsigned short *)DMA1_Y_COUNT)#define pDMA1_X_MODIFY ((volatile signed short *)DMA1_X_MODIFY)#define pDMA1_Y_MODIFY ((volatile signed short *)DMA1_Y_MODIFY)#define pDMA1_CURR_DESC_PTR (_PTR_TO_VOL_VOID_PTR DMA1_CURR_DESC_PTR)#define pDMA1_CURR_ADDR (_PTR_TO_VOL_VOID_PTR DMA1_CURR_ADDR)#define pDMA1_CURR_X_COUNT ((volatile unsigned short *)DMA1_CURR_X_COUNT)#define pDMA1_CURR_Y_COUNT ((volatile unsigned short *)DMA1_CURR_Y_COUNT)#define pDMA1_IRQ_STATUS ((volatile unsigned short *)DMA1_IRQ_STATUS)#define pDMA1_PERIPHERAL_MAP ((volatile unsigned short *)DMA1_PERIPHERAL_MAP)

Une partie du fichier defBF532.h :

/* SYSTEM & MM REGISTER BIT & ADDRESS DEFINITIONS FOR ADSP-BF532 */

#ifndef _DEF_BF532_H#define _DEF_BF532_H

#if !defined(__ADSPLPBLACKFIN__)#warning defBF532.h should only be included for 532 compatible chips#endif// include all Core registers and bit definitions#include <def_LPBlackfin.h>

/* Helper macros* usage:* P0.H = HI(UART_THR);* P0.L = LO(UART_THR);*/

#define LO(con32) ((con32) & 0xFFFF)#define lo(con32) ((con32) & 0xFFFF)#define HI(con32) (((con32) >> 16) & 0xFFFF)#define hi(con32) (((con32) >> 16) & 0xFFFF)

//******************************************************************************// System MMR Register Map//******************************************************************************// Clock and System Control (0xFFC00000 - 0xFFC000FF)

#define PLL_CTL 0xFFC00000 //PLL Control register (16-bit)#define PLL_DIV 0xFFC00004 // PLL Divide Register (16-bit)#define VR_CTL 0xFFC00008 // Voltage Regulator Control Register#define PLL_STAT 0xFFC0000C // PLL Status register (16-bit)#define PLL_LOCKCNT 0xFFC00010 // PLL Lock Count register (16-bit)#define SWRST 0xFFC00100 // Software Reset Register (16-bit)#define SYSCR 0xFFC00104 // System Configuration registe

// System Interrupt Controller (0xFFC00100 - 0xFFC001FF)#define SIC_RVECT 0xFFC00108 // Interrupt Reset Vector Address Register#define SIC_IMASK 0xFFC0010C // Interrupt Mask Register#define SIC_IAR0 0xFFC00110 // Interrupt Assignment Register 0#define SIC_IAR1 0xFFC00114 // Interrupt Assignment Register 1#define SIC_IAR2 0xFFC00118 // Interrupt Assignment Register 2#define SIC_ISR 0xFFC00120 // Interrupt Status Register#define SIC_IWR 0xFFC00124 // Interrupt Wakeup Register

// SPI Controller (0xFFC00500 - 0xFFC005FF)#define SPI_CTL 0xFFC00500 // SPI Control Register#define SPI_FLG 0xFFC00504 // SPI Flag register#define SPI_STAT 0xFFC00508 // SPI Status register#define SPI_TDBR 0xFFC0050C // SPI Transmit Data Buffer Register#define SPI_RDBR 0xFFC00510 // SPI Receive Data Buffer Register#define SPI_BAUD 0xFFC00514 // SPI Baud rate Register#define SPI_SHADOW 0xFFC00518 // SPI_RDBR Shadow Register

//// SPORT0 Controller (0xFFC00800 - 0xFFC008FF)#define SPORT0_TCR1 0xFFC00800 // SPORT0 Transmit Configuration 1 Register#define SPORT0_TCR2 0xFFC00804 // SPORT0 Transmit Configuration 2 Register#define SPORT0_TCLKDIV 0xFFC00808 // SPORT0 Transmit Clock Divider#define SPORT0_TFSDIV 0xFFC0080C // SPORT0 Transmit Frame Sync Divider#define SPORT0_TX 0xFFC00810 // SPORT0 TX Data Register#define SPORT0_RX 0xFFC00818 // SPORT0 RX Data Register#define SPORT0_RCR1 0xFFC00820 // SPORT0 Transmit Configuration 1 Register#define SPORT0_RCR2 0xFFC00824 // SPORT0 Transmit Configuration 2 Register#define SPORT0_RCLKDIV 0xFFC00828 // SPORT0 Receive Clock Divider#define SPORT0_RFSDIV 0xFFC0082C //SPORT0 Receive Frame Sync Divider

#define SPORT0_STAT 0xFFC00830 //SPORT0 Status Register

#define SPORT0_CHNL 0xFFC00834 //SPORT0 Current Channel Register

#define SPORT0_MCMC1 0xFFC00838 //SPORT0 Multi-Channel Configuration Register 1

#define SPORT0_MCMC2 0xFFC0083C //SPORT0 Multi-Channel Configuration Register 2

#define SPORT0_MTCS0 0xFFC00840 //SPORT0 Multi-Channel Transmit Select Register 0



#define SPORT0_MTCS3 0xFFC0084C //SPORT0 Multi-Channel Transmit Select Register 3

#define SPORT0_MRCS0 0xFFC00850 //SPORT0 Multi-Channel Receive Select Register 0



#define SPORT0_MRCS3 0xFFC0085C //SPORT0 Multi-Channel Receive Select Register 3

//// DMA Controller (0xFFC00C00 - 0xFFC00FFF)#define DMA0_CONFIG 0xFFC00C08 //DMA Channel 0 Configuration Register

#define DMA0_NEXT_DESC_PTR 0xFFC00C00 //DMA Channel 0 Next Descriptor PointerRegister

#define DMA0_START_ADDR 0xFFC00C04 //DMA Channel 0 Start Address Register

#define DMA0_X_COUNT 0xFFC00C10 //DMA Channel 0 X Count Register#define DMA0_Y_COUNT 0xFFC00C18 //DMA Channel 0 Y Count Register#define DMA0_X_MODIFY 0xFFC00C14 //DMA Channel 0 X Modify Register#define DMA0_Y_MODIFY 0xFFC00C1C //DMA Channel 0 Y Modify Register#define DMA0_CURR_DESC_PTR 0xFFC00C20 //DMA Channel 0 Current Descriptor PointerRegister

#define DMA0_CURR_ADDR 0xFFC00C24 //DMA Channel 0 Current Address Register

#define DMA0_CURR_X_COUNT 0xFFC00C30 //DMA Channel 0 Current X Count Register

#define DMA0_CURR_Y_COUNT 0xFFC00C38 //DMA Channel 0 Current Y Count Register

#define DMA0_IRQ_STATUS 0xFFC00C28 //DMA Channel 0 Interrupt/Status Register

#define DMA0_PERIPHERAL_MAP 0xFFC00C2C //DMA Channel 0 Peripheral Map Register

#define DMA1_CONFIG 0xFFC00C48 //DMA Channel 1 Configuration Register */

#define DMA1_NEXT_DESC_PTR 0xFFC00C40 //DMA Channel 1 Next Descriptor Pointer Register

#define DMA1_START_ADDR 0xFFC00C44 //DMA Channel 1 Start Address Register */

#define DMA1_X_COUNT 0xFFC00C50 //DMA Channel 1 X Count Register */#define DMA1_Y_COUNT 0xFFC00C58 //DMA Channel 1 Y Count Register */#define DMA1_X_MODIFY 0xFFC00C54 //DMA Channel 1 X Modify Register */#define DMA1_Y_MODIFY 0xFFC00C5C //DMA Channel 1 Y Modify Register */#define DMA1_CURR_DESC_PTR 0xFFC00C60 //DMA Channel 1 Current Descriptor Pointer

#define DMA1_CURR_ADDR 0xFFC00C64 //DMA Channel 1 Current Address Register

#define DMA1_CURR_X_COUNT 0xFFC00C70 //DMA Channel 1 Current X Count Register

#define DMA1_CURR_Y_COUNT 0xFFC00C78 //DMA Channel 1 Current Y Count Register

#define DMA1_IRQ_STATUS 0xFFC00C68 //DMA Channel 1 Interrupt/Status Register

#define DMA1_PERIPHERAL_MAP 0xFFC00C6C //DMA Channel 1 Peripheral Map Register

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