vhdl programmes.doc

8/14/2019 VHDL Programmes.doc

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Priority Encoders

VHDL

Following is the VHDL code for a 3-bit 1-of-9 Priority Encoder.

library ieee;use ieee.std_logic_1164.all;

entity priority isport ( sel : in std_logic_vector (7 downto 0);

code :out std_logic_vector (2 downto 0));end priority;arcitecture arci o! priority isbegincode "# $000$ wen sel(0) # %1% else

$001$ wen sel(1) # %1% else$010$ wen sel(2) # %1% else$011$ wen sel(&) # %1% else

$100$ wen sel(4) # %1% else$101$ wen sel(') # %1% else$110$ wen sel(6) # %1% else$111$ wen sel(7) # %1% else$$;

end arci;

VHDL (One-Hot)

Following is the VHDL code for a 3 to 8 line decoder.

library ieee

use ieee.std_logic_1164.all;

entity dec isport (sel: in std_logic_vector (2 downto 0);

res: out std_logic_vector (7 downto 0));end dec;arcitecture arci o! dec isbeginres "# $00000001$ wen sel # $000$ else

$00000010$ wen sel # $001$ else$00000100$ wen sel # $010$ else$00001000$ wen sel # $011$ else$00010000$ wen sel # $100$ else$00100000$ wen sel # $101$ else

$01000000$ wen sel # $110$ else$10000000$;

end arci;

VHDL (One-Cold)

Following is the VHDL code for a 3 to 8 line decoder.



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res: out std_logic_vector (7 downto 0));end dec;arcitecture arci o! dec isbeginres "# $11111110$ wen sel # $000$ else

$11111101$ wen sel # $001$ else$11111011$ wen sel # $010$ else$11110111$ wen sel # $011$ else$11101111$ wen sel # $100$ else$11011111$ wen sel # $101$ else$10111111$ wen sel # $110$ else$01111111$;

end arci;

IO pins Description

s!"#$% &elector

res Data '(t)(t

VHDL

Following is the VHDL code.



res: out std_logic_vector (7 downto 0));end dec;arcitecture arci o! dec isbeginres "# $00000001$ wen sel # $000$ else unused decoder output

$$ wen sel # $001$ else$00000100$ wen sel # $010$ else$00001000$ wen sel # $011$ else$00010000$ wen sel # $100$ else$00100000$ wen sel # $101$ else$01000000$ wen sel # $110$ else$10000000$;

end arci;

IO pins Description

s!"#$% &elector

res Data '(t)(t

VHDL




res: out std_logic_vector (7 downto 0));end dec;


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arcitecture arci o! dec isbeginres "# $00000001$ wen sel # $000$ else

$00000010$ wen sel # $001$ else$00000100$ wen sel # $010$ else$00001000$ wen sel # $011$ else$00010000$ wen sel # $100$ else$00100000$ wen sel # $101$ else

110 and 111 selector values are unused$$;

end arci;

VHDL Code

Following is the VHDL code for a *-to-1 1-bit +, (sing an f state/ent.


entity *u+ isport (a, b, c, d : in std_logic;

s : in std_logic_vector (1 downto 0);o : out std_logic);

end *u+;arcitecture arci o! *u+ isbeginprocess (a, b, c, d, s)begini! (s # $00$) ten o "# a;elsi! (s # $01$) ten o "# b;elsi! (s # $10$) ten o "# c;else o "# d;

end i!;end process;

end arci;

4-to-1 MUX Using C!E !t"te#ent

0he following table shows )in definitions for a *-to-1 1-bit +, (sing a ase state/ent.

IO Pins Description

a2 b2 c2 d Data n)(ts

s!1#$% +, selector

o Data '(t)(t

VHDL CodeFollowing is the VHDL code for a *-to-1 1-bit +, (sing a ase state/ent.


entity /( is port (a, b, c, d : in std_logic;

s : in std_logic_vector (1 downto 0);


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o : out std_logic);end *u+;

arcitecture arci o! *u+ isbeginprocess (a, b, c, d, s)begincase s iswen $00$ #- o "# a;wen $01$ #- o "# b;wen $10$ #- o "# c;wen oters #- o "# d;

end case;end process;

end arci;

4-to-1 MUX Using $rist"te %&''ers

0his section shows VHDL and Verilog ea/)les for a *-to-1 +( (sing tristate b(ffers

0he following table shows )in definitions for a *-to-1 1-bit +, (sing tristate b(ffers.

IO Pins Description


s!3#$% +, &elector

o Data '(t)(t

VHDL Code

Following is the VHDL code for a *-to-1 1-bit +, (sing tristate b(ffers.


entity *u+ isport (a, b, c, d : in std_logic;s : in std_logic_vector (& downto 0);o : out std_logic);

end *u+;

arcitecture arci o! *u+ isbegin

o "# a wen (s(0)#%0%) else %%;o "# b wen (s(1)#%0%) else %%;o "# c wen (s(2)#%0%) else %%;o "# d wen (s(&)#%0%) else %%;

end arci;

o 4-to-1 MUX

0he following ea/)le does not generate a *-to-1 1-bit +,2 b(t 3-to-1 +, with 1-bitlatch. 0he reason is that not all selector 4al(es were described in the f state/ent. t is

s())osed that for the s511 case2 6'6 7ee)s its old 4al(e2 and therefore a /e/ory ele/ent

is needed.

0he following table shows )in definitions for a 3-to-1 1-bit +, with a 1-bit latch.


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IO Pins Description


s!1#$% &elector

o Data '(t)(t

VHDL CodeFollowing is the VHDL code for a 3-to-1 1-bit +, with a 1-bit latch.


entity *u+ isport (a, b, c, d : in std_logic;

s : in std_logic_vector (1 downto 0);o : out std_logic);

end *u+;arcitecture arci o! *u+ isbegin

process (a, b, c, d, s)begini! (s # $00$) ten o "# a;elsi! (s # $01$) ten o "# b;elsi! (s # $10$) ten o "# c;end i!;

end process;end arci;

Logic"l !i'ters

E*"#ple 1

0he following table shows )in descri)tions for a logical shifter.

IO pins Description

D!#$% Data n)(t

&EL shift distance selector

&'!#$% Data '(t)(t

VHDL

Following is the VHDL code for a logical shifter.

library ieee;use ieee.std_logic_1164.all;use ieee.nu*eric_std.all;

entity lsi!t isport(/ : in unsigned(7 downto 0);

3 : in unsigned(1 downto 0); : out unsigned(7 downto 0));

end lsi!t;arcitecture arci o! lsi!t isbeginwit 3 select "# / wen $00$,


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/ sll 1 wen $01$,/ sll 2 wen $10$,/ sll & wen oters;

end arci;

E*"#ple +

&0 will notinfer a Logical &hifter for this ea/)le2 as not all of the selector 4al(es are)resented.

IO pins Description

D!#$% Data n)(t


&'!#$% Data '(t)(t

VHDL


library ieee;

use ieee.std_logic_1164.all;use ieee.nu*eric_std.all;


3 : in unsigned(1 downto 0); : out unsigned(7 downto 0));

end lsi!t;arcitecture arci o! lsi!t isbeginwit 3 select "# / wen $00$,

/ sll 1 wen $01$,/ sll 2 wen oters;

end arci;

E*"#ple ,

&0 will notinfer a Logical &hifter for this ea/)le2 as the 4al(e is not incre/ented by 1

for each conse(ent binary 4al(e of the selector.

IO pins Description

D!#$% Data n)(t


&'!#$% Data '(t)(t

VHDL


library ieee;use ieee.std_logic_1164.all;use ieee.nu*eric_std.all;


3 : in unsigned(1 downto 0);


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: out unsigned(7 downto 0));end lsi!t;arcitecture arci o! lsi!t isbeginwit 3 select "# / wen $00$,

/ sll 1 wen $01$,/ sll & wen $10$,/ sll 2 wen oters;

end arci;

rit#etic Oper"tions

&0 s())orts the following arith/etic o)erations#

:dders with#

o arry n

o arry '(t

o arry n;'(t

&(btractors

:dders;s(btractors

o/)arators 2 >5?

+(lti)liers

Di4iders

:dders2 &(btractors2 o/)arators and +(lti)liers are s())orted for signed and (nsigned

o)erations.Please refer to the 6&igned;,nsigned &())ort6 section of this cha)ter for /oreinfor/ation on the signed;(nsigned o)erations s())ort in VHDL.

+oreo4er2 &0 )erfor/s reso(rce sharing for adders2 s(btractors2 adders;s(btractors and

/(lti)liers.

dders !&.tr"ctors dders/!&.tr"ctors

0his section )ro4ides HDL ea/)les of adders and s(btractors

Unsigned 0-.it dder

0his s(bsection contains a VHDL and Verilog descri)tion of an (nsigned 8-bit :dder

0he following table shows )in descri)tions for an (nsigned 8-bit :dder.

IO pins Description

:!#$%2 @!#$% :dd ')erands

&,+!#$% :dd Aes(lt

VHDL


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Following is the VHDL code for an (nsigned 8-bit :dder.

library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;

entity adder is

port(5, : in std_logic_vector(7 downto 0);8 : out std_logic_vector(7 downto 0));

end adder;arcitecture arci o! adder isbegin8 "# 5 9 ;

end arci;

Unsigned 0-.it dder it C"rry In

0his section contains VHDL and Verilog descri)tions of an (nsigned 8-bit adder with

arry n.

0he following table shows )in descri)tions for an (nsigned 8-bit adder with carry.

IO pins Description

:!#$%2 @!#$% :dd ')erands

arry n

&,+!#$% :dd Aes(lt

VHDL

Following is the VHDL code for an (nsigned 8-bit adder with carry in.


use ieee.std_logic_unsigned.all;

entity adder isport(5, : in std_logic_vector(7 downto 0);

: in std_logic;8 : out std_logic_vector(7 downto 0));

end adder;arcitecture arci o! adder isbegin8 "# 5 9 9 ;

end arci;

Unsigned 0-.it dder it C"rry O&t

0he following table shows )in descri)tions for an (nsigned 8-bit adder with carry

IO pins Description

:!#$%2 @!#$% :dd ')erands

&,+!#$% :dd Aes(lt

' arry '(t

VHDL


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Following is the VHDL code for an (nsigned 8-bit adder with carry o(t.

library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arit.all;use ieee.std_logic_unsigned.all;

entity adder isport(5, : in std_logic_vector(7 downto 0);

8 : out std_logic_vector(7 downto 0); : out std_logic);

end adder;arcitecture arci o! adder issignal t*p: std_logic_vector( downto 0);begint*p "# conv_std_logic_vector(

(conv_integer(5) 9conv_integer()),


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end adder;arcitecture arci o! adder issignal t*p: std_logic_vector( downto 0);begint*p "# conv_std_logic_vector(

(conv_integer(5) 9conv_integer() 9conv_integer()),


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arcitecture arci o! subtr isbegin= "# 5 ;

end arci;

Unsigned 0-.it dder/!&.tr"ctor0he following table shows )in descri)tions for an (nsigned 8-bit adder;s(btractor.

IO pins Description

:!#$%2 @!#$% :dd;&(b ')erands

'PEA :dd;&(b &elect

&,+!#$% :dd;&(b Aes(lt

VHDL

Following is the VHDL code for an (nsigned 8-bit adder;s(btractor.

library ieee;

use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;

entity addsub isport(5, : in std_logic_vector(7 downto 0);

>=: in std_logic;= : out std_logic_vector(7 downto 0));

end addsub;arcitecture arci o! addsub isbegin= "# 5 9 wen >=#%0%

else 5 ;end arci;

end*oduleCo#p"r"tors (2 /23 32 2)

0his section contains a VHDL and Verilog descri)tion for an (nsigned 8-bit greater ore(al co/)arator.

Unsigned 0-.it 5re"ter or E6&"l Co#p"r"tor

0he following table shows )in descri)tions for a co/)arator.

IO pins Description

:!#$%2 @!#$% :dd;&(b ')erands

+P o/)arison Aes(lt

VHDL

Following is the VHDL code for an (nsigned 8-bit greater or e(al co/)arator.


entity co*par is


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port(5, : in std_logic_vector(7 downto 0);8> : out std_logic);

end co*par;arcitecture arci o! co*par isbegin8> "# %1% wen 5 -#

else %0%;end arci;

M&ltipliers

hen i/)le/enting a /(lti)lier2 the sie of the res(lting signal is e(al to the s(/ of "

o)erand lengths. f yo( /(lti)ly :


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IO pins Description

D!#$% DV ')erands

D'!#$% DV Aes(lt

VHDL

Following is the VHDL code for a Di4ision @y onstant " di4ider.library ieee;use ieee.std_logic_1164.all;use ieee.nu*eric_std.all;

entity divider isport(/ : in unsigned(7 downto 0);

/ : out unsigned(7 downto 0));end divider;arcitecture arci o! divider isbegin/ "# / @ 2;

end arci;

8eso&rce !"ring

0he goal of reso(rce sharing


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use ieee.std_logic_unsigned.all;

entity adds(b isport(5,, : in std_logic_vector(7 downto 0);

>= : in std_logic;= : out std_logic_vector(7 downto 0));

end addsub;arcitecture arci o! addsub isbegin= "# 5 9 wen >=#%0%

else 5 ;end arci;

"dder3=5=A ieee ; ieee.std_logic_1164.all ;

ieee.std_logic_arit.all ;

BCCA adder >=C(in1: B std_logic_vector(1' /DBC 0) ; in2: B std_logic_vector(1' /DBC 0) ; c_out: C std_logic ; su*: C std_logic_vector(1' /DBC 0) ) ;B/ adder ;

5=ECC= syntesiFable G adder HB >=(in1, in2) I5=53 t*p_in1: signed(16 /DBC 0) ;

I5=53 t*p_in2: signed(16 /DBC 0) ; I5=53 output: signed(16 /DBC 0) ; I5=53 c: std_logic ; HB t*p_in1 :# signed(%0% J in1) ; t*p_in2 :# signed(%0% J in2) ; output :# t*p_in1 9 t*p_in2 ;

G (output(16) # %1%) CEB c :# %1% ; 3 c :# %0% ; B/ G ;

su* "# std_logic_vector(output(1' /DBC 0)) ;

c_out "# c ; B/ >= ;B/ syntesiFable ;

counter

3=5=A ieee ; ieee.std_logic_1164.all ; ieee.std_logic_arit.all ;


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BCCA counter >=C(clK: B std_logic ; input: B std_logic_vector(11 /DBC 0) ; output: C std_logic_vector(11 /DBC 0) ; ld: B std_logic ; inc: B std_logic ; clr: B std_logic

) ;B/ counter ;

5=ECC= beavioral G counter HB generic_counter: >=(clK, input, ld, inc, clr) I5=53 t*pvar: unsigned(11 /DBC 0) ; HB G (rising_edge(clK)) CEB G (clr # %1%) CEB t*pvar :# (CE= #- %0%) ; 3G (ld # %1%) CEB

t*pvar :# unsigned(input) ; 3G (inc # %1%) CEB t*pvar :# t*pvar 9 $000000000001$ ; B/ G ; output "# std_logic_vector(t*pvar) ; B/ G ; B/ >= ;B/ beavioral ;

/esign a 2bit countdown counter3=5=A ieee ; ieee.std_logic_1164.all ; ieee.std_logic_arit.all ; ieee.std_logic_signed.all ; ieee.std_logic_unsigned.all ;

BCCA down_counter >=C(HB53 +: B std_logic ;

HB53 count : C std_logic_vector(1 /DBC 0) ;HB53 reset: B std_logic ;HB53 clK: B std_logic

) ;B/ down_counter ;

5=ECC= arc1 G down_counter HB >=(clK, +, reset) I5=53 t*p_cnt: unsigned(1 /DBC 0) ;

HB G (reset # %1%) CEB

t*p_cnt :# $00$ ; 3G rising_edge(clK) CEB


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G (+ # %1%) CEB t*p_cnt :# t*p_cnt $01$ ;

B/ G ; B/ G ; count "# std_logic_vector(t*p_cnt) ; B/ >= ;B/ arc1 ;

to & priority encoder

3=5=A ieee ; ieee.std_logic_1164.all ;

BCCA encto& >=C(HB53 input: B std_logic_vector(7 /DBC 0) ; HB53 output: C std_logic_vector(2 /DBC 0)

) ;B/ encto& ;

Eere is a case were we really need te DEB 3 don%t tinK te DCE select will worK because we want a priority encoder5=ECC= arc1 G encto& HB output "# $111$ DEB (input(7) # %1%) 3

$110$ DEB (input(6) # %1%) 3 $101$ DEB (input(') # %1%) 3 $100$ DEB (input(4) # %1%) 3 $011$ DEB (input(&) # %1%) 3 $010$ DEB (input(2) # %1%) 3 $001$ DEB (input(1) # %1%) 3 $000$ ;

B/ arc1 ;

!a.vd 5 1bit !ulladder

Heorge 3. ngel,


BCCA !a >=C( a, b : in std_logic ; cin : in std_logic ; cout : out std_logic ;


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su* : out std_logic ) ;B/ !a ;

5=ECC= arc1 G !a HB su* "# (a = b) = cin ; cout "# (a 5B/ b) = ((a = b) 5B/ cin) ;B/ arc1 ;

REGISTER


BCCA reg >=C(clK: B std_logic ; input: B std_logic_vector(1' /DBC 0) ; output: C std_logic_vector(1' /DBC 0) ; ld: B std_logic ) ;B/ reg ;

5=ECC= beavioral G reg HB generic_register: >=(clK, input, ld) HB G (rising_edge(clK)) CEB G (ld # %1%) CEB output "# input ;

B/ G ; B/ G ; B/ >= ;B/ beavioral ;

/ GlipGlop (/ booK apter 2.&.1) by DeiLun ang, 04@2001 Glip!lop is te basic co*ponent in seMuential logic design we assign input signal to te output at te clocK rising edge

library ieee ;


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use ieee.std_logic_1164.all;use worK.all;

entity d!! isport( data_in: in std_logic;

clocK: in std_logic;data_out: out std_logic

);end d!!;

arcitecture bev o! d!! isbegin

process(data_in, clocK) begin

clocK rising edge

i! (clocK#%1% and clocK%event) ten data_out "# data_in;end i!;

end process;

end bev;

NO GlipGlop wit reset (/ booK apter 2.&.1) by DeiLun ang, 04@2001 te description o! NO GlipGlop is based on !unctional trut table concurrent state*ent and signal assign*ent are using in tis e+a*ple


entity NO_GG isport ( clocK: in std_logic;

N, O: in std_logic;reset: in std_logic;P, Pbar: out std_logic

);end NO_GG;


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arcitecture bev o! NO_GG is

de!ine te use!ul signals ere

signal state: std_logic; signal input: std_logic_vector(1 downto 0);

begin

co*bine inputs into vector input "# N J O;

p: process(clocK, reset) is begin

i! (reset#%1%) ten state "# %0%;elsi! (rising_edge(clocK)) ten

co*pare to te trut table case (input) is

wen $11$ #- state "# not state;wen $10$ #- state "# %1%;wen $01$ #- state "# %0%;wen oters #- null;end case;

end i!;

end process;

concurrent state*ents P "# state; Pbar "# not state;

end bev;

nbit =egister (/ booK !igure 2.6) by DeiLun ang, 04@2001

OA D=/: concurrent, generic and range

library ieee ;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;


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entity reg is

generic(n: natural :#2);port( : in std_logic_vector(n1 downto 0);

clocK: in std_logic;load: in std_logic;clear: in std_logic;P: out std_logic_vector(n1 downto 0)

);end reg;

arcitecture bev o! reg is

signal P_t*p: std_logic_vector(n1 downto 0);

begin

process(, clocK, load, clear)

begin

i! clear # %0% ten use %range in signal assig*ent

P_t*p "# (P_t*p%range #- %0%);elsi! (clocK#%1% and clocK%event) ten i! load # %1% ten

P_t*p "# ; end i!;end i!;

end process;

concurrent state*ent P "# P_t*p;

end bev;

&bit i!t=egister@i!ter (/ booK !igure 2.6) by DeiLun ang, 04@2001

reset is ignored according to te !igure

library ieee ;use ieee.std_logic_1164.all;

entity si!t_reg isport( : in std_logic;


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clocK: in std_logic;si!t: in std_logic;P: out std_logic

);end si!t_reg;

arcitecture bev o! si!t_reg is

initialiFe te declared signal signal : std_logic_vector(2 downto 0):#$111$;

begin

process(, clocK, si!t, ) begin

everyting appens upon te clocK cangingi! clocK%event and clocK#%1% ten

i! si!t # %1% ten "# J (2 downto 1);

end i!;end i!;

end process;

concurrent assign*ent P "# (0);

end bev;

IE/3 code !or nbit counter (/ !igure 2.6) by DeiLun ang, 04@2001 tis is te beavior description o! nbit counter anoter way can be used is G8 *odel.

library ieee ;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;

entity counter is

generic(n: natural :#2);port( clocK: in std_logic;

clear: in std_logic;count: in std_logic;P: out std_logic_vector(n1 downto 0)


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);end counter;

arcitecture bev o! counter is

signal >re_P: std_logic_vector(n1 downto 0);

begin

beavior describe te counter

process(clocK, count, clear) begin

i! clear # %1% ten >re_P "# >re_P >re_P;

elsi! (clocK#%1% and clocK%event) ten i! count # %1% ten

>re_P "# >re_P 9 1;

end i!;end i!;

end process;

concurrent assign*ent state*ent P "# >re_P;

end bev;


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VHDL Code for Shift registers

0-.it !i't-Le't 8egister it Positi7e-Edge Cloc: !eri"l In "nd !eri"l

O&t

ote For this ea/)le2 &0 will infer &AL1G.

0he following table shows )in definitions for an 8-bit shift-left register with a )ositi4e-edge cloc72 serial in2 and serial o(t.

IO Pins Description

Positi4e-Edge loc7

& &erial n

&' &erial '(t)(t

VHDL Code

Following is the VHDL code for an 8-bit shift-left register with a )ositi4e-edge cloc72

serial in2 and serial o(t.


entity si!t isport(, : in std_logic;

: out std_logic);end si!t;arcitecture arci o! si!t issignal t*p: std_logic_vector(7 downto 0);beginprocess ()begini! (%event and #%1%) ten!or i in 0 to 6 loopt*p(i91) "# t*p(i);

end loop;t*p(0) "# ;end i!;

end process; "# t*p(7);

end arci;


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0-.it !i't-Le't 8egister it eg"ti7e-Edge Cloc: Cloc: En".le

!eri"l In "nd !eri"l O&t

ote For this ea/)le2 &0 will infer &AL1GEB1.

0he following table shows )in definitions for an 8-bit shift-left register with a negati4e-

edge cloc72 cloc7 enable2 serial in2 and serial o(t.IO Pins Description

egati4e-Edge loc7

& &erial n

E loc7 Enable


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Positi4e-Edge loc7

& &erial n

LA :synchrono(s lear


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entity si!t isport(, , : in std_logic;

: out std_logic);end si!t;arcitecture arci o! si!t issignal t*p: std_logic_vector(7 downto 0);beginprocess (, )begini! (%event and #%1%) teni! (#%1%) tent*p "# (oters #- %1%);

elset*p "# t*p(6 downto 0) J ;

end i!;end i!;

end process; "# t*p(7);

end arci;

0-.it !i't-Le't 8egister it Positi7e-Edge Cloc: !eri"l In "nd

P"r"llel O&t

ote For this ea/)le &0 will infer &AL1G.

0he following table shows )in definitions for an 8-bit shift-left register with a )ositi4e-

edge cloc72 serial in2 and serial o(t.

IO Pins Description

Positi4e-Edge loc7

& &erial nP'!#$% Parallel '(t)(t

VHDL Code

Following is the VHDL code for an 8-bit shift-left register with a )ositi4e-edge cloc72serial in2 and serial o(t.


entity si!t isport(, : in std_logic;

> : out std_logic_vector(7 downto 0));end si!t;arcitecture arci o! si!t issignal t*p: std_logic_vector(7 downto 0);beginprocess ()begini! (%event and #%1%) tent*p "# t*p(6 downto 0)J ;

end i!;


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end process;> "# t*p;

end arci;

0-.it !i't-Le't 8egister it Positi7e-Edge Cloc: syncrono&sP"r"llel Lo"d !eri"l In "nd !eri"l O&t

ote For this ea/)le &0 will infer &AL1G.


edge cloc72 asynchrono(s )arallel load2 serial in2 and serial o(t.

IO Pins Description

Positi4e-Edge loc7

& &erial n

:L':D :synchrono(s Parallel Load


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edge cloc72 synchrono(s )arallel load2 serial in2 and serial o(t.

IO Pins Description

Positi4e-Edge loc7

& &erial n

&L':D &ynchrono(s Parallel Load


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Following is the VHDL code for an 8-bit shift-left;shift-right register with a )ositi4e-edge

cloc72 serial in2 and serial o(t.


entity si!t is

port(, , 3GC_=HEC : in std_logic;> : out std_logic_vector(7 downto 0));

end si!t;arcitecture arci o! si!t issignal t*p: std_logic_vector(7 downto 0);beginprocess ()begini! (%event and #%1%) teni! (3GC_=HEC#%0%) tent*p "# t*p(6 downto 0) J ;

elset*p "# J t*p(7 downto 1);

end i!;end i!;

end process;> "# t*p;

end arci;

Co&nters

4-.it Unsigned Up Co&nter it syncrono&s Cle"r


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0he following table shows )in definitions for a *-bit (nsigned () co(nter with

asynchrono(s clear.

IO Pins Description

Positi4e-Edge loc7



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port(, : in std_logic;P : out std_logic_vector(& downto 0));

end counter;arcitecture arci o! counter issignal t*p: std_logic_vector(& downto 0);beginprocess ()begini! (%event and #%1%) teni! (#%1%) tent*p "# $1111$;

elset*p "# t*p 1;

end i!;end i!;

end process;P "# t*p;

end arci;

4-.it Unsigned Up Co&nter it syncrono&s Lo"d 'ro# Pri#"ry

Inp&t


asynchrono(s load fro/ )ri/ary in)(t.

IO Pins Description

Positi4e-Edge loc7

:L':D :synchrono(s Load


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elsi! (%event and #%1%) tent*p "# t*p 9 1;

end i!;


end arci;

4-.it Unsigned Up Co&nter it !yncrono&s Lo"d it " Const"nt


synchrono(s load with a constant.

IO Pins Description

Positi4e-Edge loc7

&L':D &ynchrono(s Load


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4-.it Unsigned Up Co&nter it syncrono&s Cle"r "nd Cloc:

En".le


asynchrono(s clear and cloc7 enable.

IO Pins Description

Positi4e-Edge loc7



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I!3#$% Data '(t)(t

VHDL Code

Following is the VHDL code for a *-bit (nsigned ();down co(nter with asynchrono(sclear.

library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity counter isport(, 3=, >_/DB : in std_logic;

P : out std_logic_vector(& downto 0));end counter;arcitecture arci o! counter issignal t*p: std_logic_vector(& downto 0);beginprocess (, 3=)begini! (3=#%1%) ten

t*p "# $0000$;elsi! (%event and #%1%) teni! (>_/DB#%1%) tent*p "# t*p 9 1;

elset*p "# t*p 1;

end i!;end i!;


end arci;

4-.it !igned Up Co&nter it syncrono&s 8eset

0he following table shows )in definitions for a *-bit signed () co(nter with

asynchrono(s reset.

IO Pins Description

Positi4e-Edge loc7



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end counter;arcitecture arci o! counter issignal t*p: std_logic_vector(& downto 0);beginprocess (, 3=)begini! (3=#%1%) tent*p "# $0000$;

elsi! (%event and #%1%) tent*p "# t*p 9 1;

end i!;end process;P "# t*p;

end arci;

8egisters

;lip-'lop it Positi7e-Edge Cloc:


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0he following fig(re shows a fli)-flo) with )ositi4e-edge cloc7.

0he following table shows )in definitions for a fli)-flo) with )ositi4e edge cloc7.

IO Pins DescriptionD Data n)(t

Positi4e Edge loc7

I Data '(t)(t

VHDL Code

Following is the e(i4alent VHDL code sa/)le for the fli)-flo) with a )ositi4e-edge

cloc7.


entity !lop isport(, / : in std_logic;

P : out std_logic);end !lop;arcitecture arci o! !lop isbeginprocess ()begini! (%event and #%1%) tenP "# /;

end i!;end process;

end arci;

Bote Den using IE/3, !or a positiveedge clocK instead o! using

i! (%event and #%1%) ten

yo( can also (se

i! (rising_edge()) ten

and for a negati4e-edge cloc7 yo( can (se

i! (!alling_edge()) ten

;lip-'lop it eg"ti7e-Edge Cloc: "nd syncrono&s Cle"r

0he following fig(re shows a fli)-flo) with negati4e-edge cloc7 and asynchrono(s clear.

0he following table shows )in definitions for a fli)-flo) with negati4e edge cloc7 and

asynchrono(s clear.


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IO Pins Description

D Data n)(t

egati4e-Edge loc7



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P "# /;end i!;

end i!;end process;

end arci;

4-.it 8egister it Positi7e-Edge Cloc: syncrono&s !et "nd Cloc:

En".le

0he following fig(re shows a *-bit register with )ositi4e-edge cloc72 asynchrono(s set

and cloc7 enable.

0he following table shows )in definitions for a *-bit register with )ositi4e-edge cloc72

asynchrono(s set and cloc7 enable.

IO Pins Description

D!3#$% Data n)(t

Positi4e-Edge loc7

PAE :synchrono(s &et


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L"tc it Positi7e 5"te

0he following fig(re shows a latch with )ositi4e gate.

0he following table shows )in definitions for a latch with )ositi4e gate.

IO Pins Description

D Data n)(t

Positi4e ateI Data '(t)(t

VHDL Code

Following is the e(i4alent VHDL code for a latch with a )ositi4e gate.


entity latc isport(H, / : in std_logic;

P : out std_logic);end latc;

arcitecture arci o! latc isbeginprocess (H, /)begini! (H#%1%) tenP "# /;

end i!;end process;

end arci;


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,-%it 1-o'-< Priority Encoder

ote For this ea/)le &0 /ay infer a )riority encoder. Jo( /(st (se the

priority9e*tr"ctconstraint with a 4al(e 'orceto force its inference.

8el"ted Constr"int

: related constraint is priority9e*tr"ct.

VHDL

Following is the VHDL code for a 3-bit 1-of-9 Priority Encoder.


entity priority isport ( sel : in std_logic_vector (7 downto 0);

code :out std_logic_vector (2 downto 0));end priority;arcitecture arci o! priority isbegincode "# $000$ wen sel(0) # %1% else

$001$ wen sel(1) # %1% else$010$ wen sel(2) # %1% else$011$ wen sel(&) # %1% else$100$ wen sel(4) # %1% else$101$ wen sel(') # %1% else$110$ wen sel(6) # %1% else$111$ wen sel(7) # %1% else$$;

end arci;

Unsigned 0-.it 5re"ter or E6&"l Co#p"r"tor

0he following table shows )in descri)tions for a co/)arator.

IO pins Description

:!#$%2 @!#$% :dd;&(b ')erands

+P o/)arison Aes(lt

VHDL

Following is the VHDL code for an (nsigned 8-bit greater or e(al co/)arator.


entity co*par isport(5, : in std_logic_vector(7 downto 0);

8> : out std_logic);


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end co*par;arcitecture arci o! co*par isbegin8> "# %1% wen 5 -#

else %0%;end arci;

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