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Triangle de signalisation

1 ANALYSE DU SYSTEME MIXTE ...................................................................................................................................2 1.1 EXPRESSION DU BESOIN ..................................................................................................................................................2 1.2 DIAGRAMME SAGITTAL...................................................................................................................................................2

2 PRESENTATION DE L'OBJET TECHNIQUE 1............................................................................................................2 3 ANALYSE FONCTIONNELLE DU TRIANGLE DE SIGNALISATION LUMINEUX .............................................3

3.1 ETUDE FONCTIONNELLE..................................................................................................................................................3 3.1.1 Fonction d'usage ....................................................................................................................................................3 3.1.2 Schéma fonctionnel de niveau 2 .............................................................................................................................3 3.1.3 Etude des milieux associés à l'objet technique1.....................................................................................................3

a) Milieu humain:...............................................................................................................................................................................3 b) Milieu physique: ............................................................................................................................................................................3 c) Milieu économique: .......................................................................................................................................................................3 d) Milieu technique: ...........................................................................................................................................................................3

3.2 ETUDE FONCTIONNELLE DE 1ER DEGRE...........................................................................................................................4 3.2.1 SCHEMA FONCTIONNEL DE 1er DEGRE .........................................................................................................4

3.3 ETUDE FONCTIONNELLE DE 2ND DEGRE ..........................................................................................................................5 3.3.1 Schéma fonctionnel de degré 2...............................................................................................................................5 3.3.2 Définition des entrées/sorties .................................................................................................................................6

4 ETUDE STRUCTURELLE ................................................................................................................................................7 4.1 SCHEMA STRUCTUREL.....................................................................................................................................................7 4.2 NOMENCLATURE.............................................................................................................................................................8 4.3 DOCUMENTS DE FABRICATION ........................................................................................................................................9

5 DOCUMENTATION TECHNIQUE................................................................................................................................10


1 Analyse du système mixte

1.1 Expression du besoin Lors de travaux sur la chaussée, les usagers de la route doivent être avertis du chantier qu'ils vont rencontrer, afin qu'ils limitent leur vitesse et qu'ils ne soient pas surpris par l'encombrement de la route. Une signalisation lumineuse avertira l'automobiliste de plus loin et attirera plus fortement son attention.

1.2 Diagramme sagittal

usagers de

la routesignalant un chantier

triangle de signalisationlumineux

O.T.1

environnement

chantiervisualisation

info.J/N

batterie de véhicule

O.T.2

info.

12V/24V

ouvrier de

information M/A

information lumineuseet choix du motif

2 Présentation de l'objet technique 1


3 Analyse fonctionnelle du triangle de signalisation lumineux

3.1 Etude fonctionnelle

3.1.1 Fonction d'usage Le triangle de signalisation lumineux réalise les fonctions suivantes:

• Élaborer une commande d'allumage des lampes en fonction du motif choisit, de la luminosité de l'environnement et du type de batterie.

• Signaler de façon lumineuse un éventuel chantier aux usagers de la route.

3.1.2 Schéma fonctionnel de niveau 2

d'allumage des lampes

environnement

cmde d'allumage

des lampes

signalisation

lumineuseinfo.

lumineuse usagers dela route

ouvrier info.M/A

info. J/NO.T.1

batterieinformation 12V/24V

élaboration d'une cmde

ouvrier de chantier

choix du motif

3.1.3 Etude des milieux associés à l'objet technique1

a) Milieu humain: • Simplicité d'utilisation. • Détermination du motif effectué en usine, en accord avec le client. • Diminution de l'intensité lumineuse la nuit pour éviter les éblouissements.

b) Milieu physique: • L'électronique étant logée dans la carcasse du triangle, il en résulte des contraintes dues à l'environnement

thermique (température ambiante avoisinant 60°C en été). • Électronique enrobée de résine et protégée contre les courts-circuits. • Résistant aux chocs.

c) Milieu économique: • Reconnaissance et adaptation automatique au type de batterie 12V ou 24V. • Motif lumineux facilement modifiable à la commande. • Faible coût de revient.

d) Milieu technique: • Source d'énergie = batterie 12V ou 24V. • Lampe à iode 12V/55W uniquement.


3.2 Etude fonctionnelle de 1er degré

3.2.1 SCHEMA FONCTIONNEL DE 1er DEGRE

élaboration de lacommande d'allumagedes lampes

F.P.1 F.P.2

signalisationlumineuse

identification dutype de batterie

F.P.3

jour / nuitF.P.4

3

information J/N

information 12V / 24Vinfo. 12V/24V

info. J/N

O.T.1

commande d'allumage

des lampes

information

lumineusechoix d'un motif parmi 8

captage


3.3 Etude fonctionnelle de 2nd degré

3.3.1 Schéma fonctionnel de degré 2

F.S.4.1

info J/N

protection contre les inversions

F.S.3.1

énergie

électrique

12V/24V

identificationde la tension12V ou 24V

F.S.3.2

captage J/N J/N

BAT

production d'unsignal rectangulaire

F.S.1.1

Productiond’adresses

F.S.1.2

h A0-A9

mémorisation

des informations

de commande

des lampes

F.S.1.3

3

10

VA

amplification

F.S.2.1

conversionénergie électrique/énergie lumineuse

F.S.2.2

S0

S1

S0'

S1'

information

lumineuse

A12-A13-A14

A10

A11

Choix d'un motif parmi 8

de polarité et détection du niveaude charge de la batterie

de puissance

F.aVoVA

R.A.Z


3.3.2 Définition des entrées/sorties info.J/N : Information : intensité lumineuse ambiante. J/N (A10) : Information logique relative à l'éclairement ambiant. E.E (12V/24V) : tension de batterie alimentant le triangle pouvant atteindre 14,5V pour une batterie de 12V et 28V pour une batterie de 24V. VA: tension d'alimentation provenant de la batterie. BAT (A11): information logique pour la détection d'une batterie de 12V ou 24V. Vo : tension régulée à 5V permettant d'alimenter les circuits logiques. A12, A13, A14: Information numérique: mot binaire de 3 bits qui permet la sélection d'un motif parmi 8.

A14 A13 A12 motifs 0 0 0 Modèle A 0 0 1 Modèle B ou C 0 1 0 Non utilisé 0 1 1 Non utilisé 1 0 0 Non utilisé 1 0 1 Non utilisé 1 1 0 Non utilisé 1 1 1 Non utilisable Identification mémoire

h : ddp rectangulaire d'amplitude (0;5V). A0 à A9 : Information numérique: mot binaire de 10 bits. Chaque mot correspond à une case mémoire qui renferme un nombre binaire de 8 bits. Le balayage des combinaisons $000 à $3FF détermine la période d'allumage et de découpage des lampes. S0 : Information logique qui commande l'allumage des lampes L1, L2, L3. S0 est une valeur mémorisée et correspond au bit de poids faible de l'octet. Lors du balayage des combinaisons des adresses A0 à A9, le niveau logique en S0 détermine l'allumage et l'intensité lumineuse des lampes L1, L2, L3. RAZ : Information logique permet la remise à zéro du nombre (A9…A0)2 .


4 Etude structurelle

4.1 Schéma structurel

1Q12

10

11 RST

12Q913Q8

14Q10 15Q11

2Q63Q5

4Q7

5Q46Q37Q29Q1

f


4.2 Nomenclature RefDes Type Value -------------------- -------------------- --------------- C1 C2 10n C2 C2 22u C3 C1 22n C4 C2_POL 100u C5 C2_POL 1u C6 C2_POL 1u C7 C2 100n C8 C2 100n D1 1N4148 D2 1N4148 D3 ZENER12V 12v D4 1N4148 D5 ZENER9.1V 9.1V D6 ZENER9.1V 9.1V D7 1N4001 D8 ZENER4.7V 4.7V D9 ZENER9.1V 9.1V D10 ZENER4.7V 4.7V J1 BORNE1 J2 BORNE1 J3 DOUILLE4 J4 DOUILLE4 J5 PTEST J6 PTEST J7 PTEST J8 PTEST J9 PTEST J10 PTEST J11 PTEST J12 BORNE1 J13 BORNE1 L1 LAMPE L2 LAMPE L3 LAMPE P1 POT3T 2.2Meg P2 POT3T 470k R1 R1 100K R2 R1 0 R3 R1 100k R4 R2 4.7k R5 R2 1K R6 R2 100k R8 R2 100k R9 R2 100k R10 R2 100k R11 R2 3.3k R12 R2 1Meg R13 R2 100K R14 R2 22K R15 R2 4.7K R16 R2 4.7k R17 R1 10k R18 R2 3.3k S1 INVERSEUR S2 INVERSEUR S3 INVERSEUR

RefDes Type Value -------------------- -------------------- --------------- T1 BC548A T2 SFH309 T3 BC548A T4 BC558B U1 CD4093BCN U2 HCC4040BF U3 IRF540 U4 ZVP2106A U5 HN58C256 U6 78L05


4.3 Documents de fabrication

Triangles rabattables pour véhicules Triangles rabattables pour véhicules

• Film Diamond Grade fl uo • Symbole autre que AK5 • Triangles de dimensions 1000 mm• Relevage électrique seul• Triangles pendulaires pour camions bennes

Nous sommes à votre disposition pour étudiertoute fabrication particulière !

SYMBOLES

Triangles pour véhicules symbole AK5

r : 500 r : 700 Consommation

LEDs Ø 60 Code Référence Prix Code Référence Prix Jour Nuit

Relevage(1) Doubleface

T1 808560035 TML124/500T1 389 € 808561035 TML124/700T1 474 €

12 V : 0,3 A

24 V : 0,15 A

12 V : 0,15 A

24 V : 0,07 A

manuel T2 808560036 TML124/500T2 431 € 808561036 TML124/700T2 562 €

Relevage Doubleface

T1 808562035 TML500ELECT1 678 € 808563035 TML700ELECT1 793 €

électrique T2 808562036 TML500ELECT2 719 € 808563036 TML700ELECT2 882 €

Fixation simpleface

T1 808564035 TUML124/500T1 281 € 808565035 TUML124/700T1 366 € 12 V : 0,15 A

24 V : 0,07 A

12 V : 0,07 A

24 V : 0,04 Arail arrière T2 808564036 TUML124/500T2 302 € 808565036 TUML124/700T2 410 €

Simple face TML500/700 Moins value -89 € Moins value -89 €

XENON Ø 60 Code Référence Prix Code Référence PrixRelevage(1) Double

faceT1 808500 TNX124/500T1 427 € 808501 TNX124/700T1 531 €

12 V : 1,4 A

24 V : 0,7 A

12 V : 0,8 A

24 V : 0,4 A

manuel T2 808500045 TNX124/500T2 469 € 808501045 TNX124/700T2 620 €

Relevage Doubleface

T1 808503 TNX500ELECT1 791 € 808504 TNX700ELECT1 926 €

électrique T2 808503045 TNX500ELECT2 832 € 808504045 TNX700ELECT2 1015 €

Fixation simpleface

T1 808506 TUX124/500T1 317 € 808507 TUX124/700T1 412 € 12 V : 0,7 A

24 V : 0,04 A

12 V : 0,4 A

24 V : 0,2 Arail arrière T2 808506035 TUX124/500T2 338 € 808507035 TUX124/700T2 456 €

Simple face TNX500/700 Moins value -74 € Moins value -74 €

IODE Ø 60 Code Référence Prix Code Référence PrixRelevage(1) Double

faceT1 808542 TMO124/500T1 294 € 808543 TMO124/700T1 384 €

12 V : 6,8 A

24 V : 3,4 A

12 V : 3,4A

24 V : 1,7A

manuel T2 808542045 TMO124/500T2 335 € 808543045 TMO124/700T2 473 €

Relevage Doubleface

T1 808548 TMO500ELECT1 657 € 808549 TMO700ELECT1 779 €

électrique T2 808548045 TMO500ELECT2 698 € 808549045 TMO700ELECT2 867 €

Fixation simpleface

T1 808509 TUMO124/500T1 291 € 808510 TUMO124/700T1 381 € 12 V : 6,8 A

24 V : 3,4 A

12 V : 3,4 A

24 V : 1,7 Arail arrière T2 808509045 TUMO124/500T2 312 € 808510045 TUMO124/700T2 425 €

Simple face TMO500/700 Moins value -6 € Moins value -6 €

(1) Le kit de rabattement est à commander séparémentAccessoires Code Référence Prix

inter avec voyant 12 V (10 A max) 812199 INT/VOY12 12 €

inter avec voyant 24 V (10 A max) 812197 INT/VOY24 12 €

prise allume-cigares 811400 P/AC 8 €

kit de rabattement 809356 K/RAB 23 €

plaque de fi xation r 500 809355 FIX/TP500 21 €

plaque de fi xation r 700 809357 FIX/TP700 28 €

embase magnétique r 500 809613 MAG/TP500 63 €

embase magnétique r 700 809614 MAG/TP700 73 €

AK17 AK30AK2 AK3 AK4 AK5 AK31AK14 AK22

Extrait du Catalogue 2005275, rue de Clermont - ZA la Vatine - F 60000 BEAUVAISTél. : 03 44 10 33 90 - Fax : 03 44 10 33 99 - Email : [email protected] - www.franclair.com

Tarifs en Euros hors taxes - départ usine

TL/F/5216

MM

54H

C4020/M

M74H

C4020

14-S

tage

Bin

ary

Counte

rM

M54H

C4040/M

M74H

C4040

12-S

tage

Bin

ary

Counte

r

December 1988

MM54HC4020/MM74HC402014-Stage Binary CounterMM54HC4040/MM74HC404012-Stage Binary Counter

General DescriptionThe MM54HC4020/MM74HC4020, MM54HC4040/

MM74HC4040, are high speed binary ripple carry counters.

These counters are implemented utilizing advanced silicon-

gate CMOS technology to achieve speed performance simi-

lar to LS-TTL logic while retaining the low power and high

noise immunity of CMOS.

The ’HC4020 is a 14 stage counter and the ’HC4040 is a 12-

stage counter. Both devices are incremented on the falling

edge (negative transition) of the input clock, and all their

outputs are reset to a low level by applying a logical high on

their reset input.

These devices are pin equivalent to the CD4020 and

CD4040 respectively. All inputs are protected from damage

due to static discharge by protection diodes to VCC and

ground.

FeaturesY Typical propagation delay: 16 nsY Wide operating voltage range: 2–6VY Low input current: 1 mA maximumY Low quiescent current: 80 mA maximum (74HC Series)Y Output drive capability: 10 LS-TTL loads

Connection Diagrams

Dual-In-Line Packages

’HC4020

TL/F/5216–1

’HC4040

TL/F/5216–3

Order Number MM54HC4020/4040 or MM74HC4020/4040

C1995 National Semiconductor Corporation RRD-B30M105/Printed in U. S. A.

Absolute Maximum Ratings (Notes 1 & 2)

If Military/Aerospace specified devices are required,

please contact the National Semiconductor Sales

Office/Distributors for availability and specifications.

Supply Voltage (VCC) b0.5 to a7.0V

DC Input Voltage (VIN) b1.5 to VCCa1.5V

DC Output Voltage (VOUT) b0.5 to VCCa0.5V

Clamp Diode Current (ICD) g20 mA

DC Output Current, per pin (IOUT) g25 mA

DC VCC or GND Current, per pin (ICC) g50 mA

Storage Temperature Range (TSTG) b65§C to a150§CPower Dissipation (PD)

(Note 3) 600 mW

S.O. Package only 500 mW

Lead Temperature (TL)

(Soldering 10 seconds) 260§C

Operating ConditionsMin Max Units

Supply Voltage (VCC) 2 6 V

DC Input or Output Voltage 0 VCC V

(VIN, VOUT)

Operating Temp. Range (TA)

MM74HC b40 a85 §CMM54HC b55 a125 §C

Input Rise or Fall Times

VCCe2.0V(tr, tf) 1000 ns

VCCe4.5V 500 ns

VCCe6.0V 400 ns

DC Electrical Characteristics (Note 4)

TAe25§C74HC 54HC

Symbol Parameter Conditions VCC TAeb40 to 85§C TAeb55 to 125§CUnits

Typ Guaranteed Limits

VIH Minimum High Level Input 2.0V 1.5 1.5 1.5 V

Voltage 4.5V 3.15 3.15 3.15 V

6.0V 4.2 4.2 4.2 V

VIL Maximum Low Level Input 2.0V 0.5 0.5 0.5 V

Voltage** 4.5V 1.35 1.35 1.35 V

6.0V 1.8 1.8 1.8 V

VOH Minimum High Level Output VINeVIH or VIL

Voltage lIOUTls20 mA 2.0V 2.0 1.9 1.9 1.9 V

4.5V 4.5 4.4 4.4 4.4 V

6.0V 6.0 5.9 5.9 5.9 V

VINeVIH or VIL

lIOUTls4.0 mA 4.5V 4.2 3.98 3.84 3.7 V

lIOUTls5.2 mA 6.0V 5.7 5.48 5.34 5.2 V

VOL Maximum Low Level Output VINeVIH or VIL

Voltage lIOUTls20 mA 2.0V 0 0.1 0.1 0.1 V

4.5V 0 0.1 0.1 0.1 V

6.0V 0 0.1 0.1 0.1 V

VINeVIH or VIL

lIOUTls4.0 mA 4.5V 0.2 .26 0.33 0.4 V

lIOUTls5.2 mA 6.0V 0.2 .26 0.33 0.4 V

IIN Maximum Input Current VINeVCC or GND 6.0V g0.1 g1.0 g1.0 mA

ICC Maximum Quiescent Supply VINeVCC or GND 6.0V 8.0 80 160 mA

Current IOUTe0 mA

Note 1: Maximum Ratings are those values beyond which damage to the device may occur.

Note 2: Unless otherwise specified all voltages are referenced to ground.

Note 3: Power Dissipation temperature derating Ð plastic ‘‘N’’ package: b12 mW/§C from 65§C to 85§C; ceramic ‘‘J’’ package: b12 mW/§C from 100§C to 125§C.

Note 4: For a power supply of 5V g10% the worst case output voltages (VOH, and VOL) occur for HC at 4.5V. Thus the 4.5V values should be used when

designing with this supply. Worst case VIH and VIL occur at VCCe5.5V and 4.5V respectively. (The VIH value at 5.5V is 3.85V.) The worst case leakage current (IIN,

ICC, and IOZ) occur for CMOS at the higher voltage and so the 6.0V values should be used.

**VIL limits are currently tested at 20% of VCC. The above VIL specification (30% of VCC) will be implemented no later than Q1, CY’89.

2

AC Electrical Characteristics VCCe5V, TAe25§C, CLe15 pF, tretfe6 ns

Symbol Parameter Conditions TypGuaranteed

UnitsLimit

fMAX Maximum Operating Frequency 50 30 MHz

tPHL, tPLH Maximum Propagation (Note 5) 17 35 ns

Delay Clock to Q

tPHL Maximum Propagation 16 40 ns

Delay Reset to any Q

tREM Minimum Reset 10 20 ns

Removal Time

tW Minimum Pulse Width 10 16 ns

AC Electrical Characteristics VCCe2.0V to 6.0V, CLe50 pF, tretfe6 ns (unless otherwise specified)

TAe25§C74HC 54HC

Symbol Parameter Conditions VCC TAeb40 to 85§C TAeb55 to 125§C Units

Typ Guaranteed Limits

fMAX Maximum Operating 2.0V 10 6 5 4 MHz

Frequency 4.5V 40 30 24 20 MHz

6.0V 50 35 28 24 MHz

tPHL, tPLH Maximum Propagation 2.0V 80 210 265 313 ns

Delay Clock to Q1 4.5V 21 42 53 63 ns

6.0V 18 36 45 53 ns

TPHL, tPLH Maximum Propagation 2.0V 80 125 156 188 ns

Delay Between Stages 4.5V 18 25 31 38 ns

from Qn to Qna1 6.0V 15 21 26 31 ns

tPHL Maximum Propagation 2.0V 72 240 302 358 ns

Delay Reset to any Q 4.5V 24 48 60 72 ns

(’4020 and ’4040) 6.0V 20 41 51 61 ns

tREM Minimum Reset 2.0V 100 126 149 ns

Removal Time 4.5V 20 25 50 ns

6.0V 16 21 25 ns

tW Minimum Pulse Width 2.0V 90 100 120 ns

4.5V 16 20 24 ns

6.0V 14 18 20 ns

tTLH, tTHL Maximum 2.0V 30 75 95 110 ns

Output Rise 4.5V 10 15 19 22 ns

and Fall Time 6.0V 9 13 16 19 ns

tr, tf Maximum Input Rise and 1000 1000 1000 ns

Fall Time 500 500 500 ns

400 400 400 ns

CPD Power Dissipation (per package) 55 pF

Capacitance (Note 6)

CIN Maximum Input 5 10 10 10 pF

Capacitance

Note 5: Typical Propagation delay time to any output can be calculated using: tP e17a12(N–1) ns; where N is the number of the output, QW, at VCCe5V.

Note 6: CPD determines the no load dynamic power consumption, PDeCPD VCC2 faICC VCC, and the no load dynamic current consumption, ISeCPD VCC faICC.

3

Logic Diagrams

MM54HC4020/MM74HC4020

TL/F/5216–5

MM54HC4040/MM74HC4040

TL/F/5216–7

4

Timing Diagram

TL/F/5216–11

5

Physical Dimensions inches (millimeters)

Order Number MM54HC4020J, MM54HC4024J, MM54HC4040J,

MM74HC4020J, MM74HC4024J, or MM74HC4040J

NS Package J14A

6

Physical Dimensions inches (millimeters) (Continued)

Order Number MM54HC4020J, MM54HC4024J, MM54HC4040J,

MM74HC4020J, MM74HC4024J, or MM74HC4040J

NS Package J16A

Order Number MM74HC4020N, MM74HC4024N or MM74HC4040N

NS Package N14A

7

MM

54H

C4020/M

M74H

C4020

14-S

tage

Bin

ary

Counte

rM

M54H

C4040/M

M74H

C4040

12-S

tage

Bin

ary

Counte

rPhysical Dimensions inches (millimeters) (Continued)

Order Number MM74HC4020N, MM74HC4024N or MM74HC4040N

NS Package N16E

LIFE SUPPORT POLICY

NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT

DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL

SEMICONDUCTOR CORPORATION. As used herein:

1. Life support devices or systems are devices or 2. A critical component is any component of a life

systems which, (a) are intended for surgical implant support device or system whose failure to perform can

into the body, or (b) support or sustain life, and whose be reasonably expected to cause the failure of the life

failure to perform, when properly used in accordance support device or system, or to affect its safety or

with instructions for use provided in the labeling, can effectiveness.

be reasonably expected to result in a significant injury

to the user.

National Semiconductor National Semiconductor National Semiconductor National SemiconductorCorporation Europe Hong Kong Ltd. Japan Ltd.1111 West Bardin Road Fax: (a49) 0-180-530 85 86 13th Floor, Straight Block, Tel: 81-043-299-2309Arlington, TX 76017 Email: cnjwge@ tevm2.nsc.com Ocean Centre, 5 Canton Rd. Fax: 81-043-299-2408Tel: 1(800) 272-9959 Deutsch Tel: (a49) 0-180-530 85 85 Tsimshatsui, KowloonFax: 1(800) 737-7018 English Tel: (a49) 0-180-532 78 32 Hong Kong

Fran3ais Tel: (a49) 0-180-532 93 58 Tel: (852) 2737-1600Italiano Tel: (a49) 0-180-534 16 80 Fax: (852) 2736-9960

National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.

Order this document by MCT7800/D

THREE-TERMINALPOSITIVE FIXED

VOLTAGE REGULATORS

Pin 1. Input2. Ground3. Output

STANDARD APPLICATION

A common ground is required between theinput and the output voltages. The input voltagemust remain typically 2.0 V above the outputvoltage even during the low point on the inputripple voltage.

XX, these two digits of the type number indicate nominal voltage.

** Cin is required if regulator is located anappreciable distance from power supply filter.

** Some CO is recommended for stability; it doesimprove transient response. Values less than0.1 µF could cause instability.

MCT78XXInput

Cin*0.33 µF

CO**

Output

T SUFFIXPLASTIC PACKAGE

CASE 221A

Heatsink surfaceconnected to Pin 2.

D2T SUFFIXPLASTIC PACKAGE

CASE 936(D2PAK)

3

12

31 2

Heatsink surface (shown as terminal 4 incase outline drawing) is connected to Pin 2.

1MCT7800MOTOROLA

These voltage regulators are monolithic integrated circuits designed asfixed-voltage regulators for a wide variety of applications including local,on-card regulation. These regulators employ internal current limiting,thermal shutdown, and safe-area compensation. With adequate heatsinkingthey can deliver output currents in excess of 1.0 A. Although designedprimarily as fixed voltage regulators, these devices can be used withexternal components to obtain adjustable voltages and currents.

• Output Current in Excess of 1.0 A

• No External Components Required

• Internal Thermal Overload Protection

• Internal Short Circuit Current Limiting

• Output Transistor Safe-Area Compensation

• Output Voltage Offered with a 4% Tolerance

• Available in Surface Mount D2PAK and Standard 3-Lead TransistorPackages

This MCT-prefixed device is intended to be a possible replacement for the similardevice with the MC-prefix. Because the MCT device originates from different sourcematerial, there may be subtle differences in typical parameter values orcharacteristic curves. Due to the diversity of potential applications, Motorola can notassure identical performance in all circuits. Motorola recommends that thecustomer qualify the MCT-prefixed device in each potential application.

DEVICE TYPE/NOMINAL OUTPUT VOLTAGE

MCT7805MCT7806MCT7808MCT7809

5.0 V6.0 V8.0 V9.0 V

MCT7812MCT7815MCT7818MCT7824

12 V15 V18 V24 V

ORDERING INFORMATION

DeviceOutput Voltage

ToleranceTested Operating

Temperature Range Package

MCT78XXBD2T

4%

TJ = – 40° to +125°CSurface Mount

MCT78XXBT4%

TJ = – 40° to +125°CInsertion Mount

MCT78XXCD2T4%

TJ = 0° to +125°CSurface Mount

MCT78XXCTTJ = 0° to +125°C

Insertion Mount

XX indicates nominal voltage. Motorola, Inc. 1994 Rev 3

MCT7800

MCT78002

MOTOROLA

MAXIMUM RATINGS (TA = +25°C, unless otherwise noted.)

Rating Symbol Value Unit

Input Voltage VI 35 Vdc

Power DissipationCase 221A

TA = +25°C PD Internally Limited W

Thermal Resistance, Junction-to-Ambient θJA 65 °C/W

Thermal Resistance, Junction-to-Case θJC 5.0 °C/W

Case 936 (D2PAK)

TA = +25°C PD Internally Limited W

Thermal Resistance, Junction-to-Ambient θJA 70 °C/W

Thermal Resistance, Junction-to-Case θJC 5.0 °C/W

Storage Junction Temperature Range Tstg – 65 to +150 °C

Operating Junction Temperature TJ +150 °C

Representative Schematic Diagram

100 500

3.3 k

2.7 k

500

1.4 k

100 100 10 k

Input

Output

Gnd

240

200 0.3

6.0 k 2.0 k

30 pF28 k

6.0 k 1.0 k 5.0 k

0.25 k

5.0 k

This device contains 19 active transistors.

MCT7800

3MCT7800MOTOROLA

ELECTRICAL CHARACTERISTICS (Vin = 10 V, IO = 500 mA, TJ = Tlow to Thigh [Note 1], unless otherwise noted.)

MCT7805B MCT7805C

Characteristics Symbol Min Typ Max Min Typ Max Unit

Output Voltage (TJ = +25°C) VO 4.8 5.0 5.2 4.8 5.0 5.2 Vdc

Output Voltage (5.0 mA ≤ IO ≤ 1.0 A, PO ≤15 W)7.0 Vdc ≤ Vin ≤ 20 Vdc8.0 Vdc ≤ Vin ≤ 20 Vdc

VO—

4.75—5.0

—5.25

4.75—

5.0—

5.25—

Vdc

Line Regulation, TJ = +25°C (Note 2)7.0 Vdc ≤ Vin ≤ 25 Vdc8.0 Vdc ≤ Vin ≤ 12 Vdc

Regline——

7.02.0

10050

——

7.02.0

10050

mV

Load Regulation, TJ = +25°C (Note 2)5.0 mA ≤ Vin ≤ 1.5 A250 mA ≤ Vin ≤ 750 mA

Regload——

2.01.5

10050

——

2.01.5

10050

mV

Quiescent Current (TJ = +25°C) IB — 5.5 8.0 — 5.5 8.0 mA

Quiescent Current Change7.0 Vdc ≤ Vin ≤ 25 Vdc8.0 Vdc ≤ Vin ≤ 25 Vdc5.0 mA ≤ IO ≤ 1.0 A

∆IB———

———

—1.30.5

———

———

1.3—0.5

mA

Ripple Rejection8.0 Vdc ≤ Vin ≤ 18 Vdc, f = 120 Hz

RR— 65 — — 65 —

dB

Dropout Voltage (IO = 1.0 A, TJ = +25°C) VI – VO — 2.0 — — 2.0 — Vdc

Output Noise Voltage (TA = +25°C)10 Hz ≤ f ≤ 100 kHz

Vn— 10 — — 10 —

µV/VO

Output Resistance f = 1.0 kHz rO — 1.3 — — 1.3 — mΩ

Short Circuit Current Limit (TA = +25°C)Vin = 35 Vdc

ISC— 0.2 — — 0.2 —

A

Peak Output Current (TJ = +25°C) Imax — 2.2 — — 2.2 — A

Average Temperature Coefficient of Output Voltage TCVO — 0.5 — — 0.5 — mV/°C


MCT7806B MCT7806C




VO—5.7

—6.0

—6.3

5.7—

6.0—

6.3—

Vdc


Regline——

7.02.0

12060

——

7.02.0

12060

mV


Regload——

2.01.5

12060

——

2.01.5

12060

mV



∆IB———

———

—1.30.5

———

———

1.3—0.5

mA

Ripple Rejection9.0 Vdc ≤ Vin ≤ 19 Vdc, f = 120 Hz

RR— 65 — — 65 —

dB

NOTES: 1. Tlow = 0°C for MCT78XXC Thigh = +125°C for MCT78XXB, C. When the junction temperature exceeds +125°C, internal current limiting = – 40°C for MCT78XXB will reduce the output current to less than 1.0 A at a VI–VO of 15 V or

greater. The MC7800 die will supply more current under the same conditions.

2. Load and line regulation are specified at constant junction temperature. Changes in VO due to heating effects must be taken into account separately.Pulse testing with low duty cycle is used.

MCT7800

MCT78004

MOTOROLA

ELECTRICAL CHARACTERISTICS (continued) (Vin = 11 V, IO = 500 mA, TJ = Tlow to Thigh [Note 1], unless otherwise noted.)

MCT7806B MCT7806C




Vn— 10 — — 10 —

µV/VO

Output Resistance f = 1.0 kHz rO — 1.3 — — 1.3 — mΩ


ISC— 0.2 — — 0.2 —

A


Average Temperature Coefficient of Output Voltage TCVO — –0.8 — — –0.8 — mV/°C


MCT7808B MCT7808C




VO—7.6

—8.0

—8.4

7.6—

8.0—

8.4—

Vdc

Line Regulation, TJ = +25°C (Note 2)10.5 Vdc ≤ Vin ≤ 25 Vdc11 Vdc ≤ Vin ≤ 17 Vdc

Regline——

7.02.0

16080

——

7.02.0

16080

mV

Load Regulation, TJ = +25°C (Note 2)5.0 mA ≤ IO ≤ 1.5 A250 mA ≤ IO ≤ 750 mA

Regload——

2.01.5

16080

——

2.01.5

16080

mV



∆IB———

———

—1.00.5

———

———

1.0—0.5

mA

Ripple Rejection11.5 Vdc ≤ Vin ≤ 21.5 Vdc, f = 120 Hz

RR— 63 — — 63 —

dB



Vn— 10 — — 10 —

µV/VO

Output Resistance f = 1.0 kHz rO — 18 — — 18 — mΩ


ISC— 0.2 — — 0.2 —

A


Average Temperature Coefficient of Output Voltage TCVO — –0.8 — — –0.8 — mV/°CNOTES: 1. Tlow = 0°C for MCT78XXC Thigh = +125°C for MCT78XXB, C. When the junction temperature exceeds +125°C, internal current limiting = – 40°C for MCT78XXB will reduce the output current to less than 1.0 A at a VI–VO of 15 V or

greater. The MC7800 die will supply more current under the same conditions.2. Load and line regulation are specified at constant junction temperature. Changes in VO due to heating effects must be taken into account separately.

Pulse testing with low duty cycle is used.

MCT7800

5MCT7800MOTOROLA


MCT7809B MCT7809C




VO—

8.55—9.0

—9.45

8.55—

9.0—

9.45—

Vdc


Regline——

8.04.0

5025

——

8.04.0

5025

mV


Regload——

3.02.0

5025

——

3.02.0

5025

mV



∆IB———

———

—1.00.5

———

———

1.0—0.5

mA


RR— 62 — — 62 —

dB



Vn— 10 — — 10 —

µV/VO



ISC— 0.2 — — 0.2 —

A




MCT7812B MCT7812C


Output Voltage (TJ = +25°C) VO 11.5 12 12.5 11.5 12 12.5 Vdc


VO—

11.4—12

—12.6

11.4—

12—

12.6—

Vdc


Regline——

105.0

240120

——

105.0

240120

mV


Regload——

3.02.0

240120

——

3.02.0

240120

mV


Quiescent Current Change14.5 Vdc ≤ Vin ≤ 30 Vdc15 Vdc ≤ Vin ≤ 30 Vdc5.0 mA ≤ IO ≤ 1.0 A

∆IB———

———

—1.00.5

———

———

1.0—0.5

mA




MCT7800

MCT78006

MOTOROLA

ELECTRICAL CHARACTERISTICS (continued) (Vin = 19 V, IO = 500 mA, TJ = Tlow to Thigh [Note 1], unless otherwise noted.)

MCT7812B MCT7812C


Ripple Rejection15 Vdc ≤ Vin ≤ 25 Vdc, f = 120 Hz

RR— 62 — — 62 —

dB



Vn— 10 — — 10 —

µV/VO



ISC— 0.2 — — 0.2 —

A




MCT7815B MCT7815C




VO—

14.25—15

—15.75

14.25—

15—

15.75—

Vdc


Regline——

115.0

300150

——

115.0

300150

mV


Regload——

3.02.0

300150

——

3.02.0

300150

mV



∆IB———

———

—1.00.5

———

———

1.0—0.5

mA


RR— 60 — — 60 —

dB



Vn— 10 — — 10 —

µV/VO



ISC— 0.2 — — 0.2 —

A






MCT7800

7MCT7800MOTOROLA


MCT7818B MCT7818C



Output Voltage (5.0 mA ≤ IO ≤ 1.0 A, PO ≤15 W)21 Vdc ≤ Vin ≤ 33 Vdc22 Vdc ≤ Vin ≤ 33 Vdc

VO—

17.1—18

—18.9

17.1—

18—

18.9—

Vdc

Line Regulation, TJ = +25°C (Note 2)21 Vdc ≤ Vin ≤ 33 Vdc24 Vdc ≤ Vin ≤ 30 Vdc

Regline——

115.0

360180

——

115.0

360180

mV


Regload——

4.03.0

360180

——

4.03.0

360180

mV


Quiescent Current Change21 Vdc ≤ Vin ≤ 33 Vdc22 Vdc ≤ Vin ≤ 33 Vdc5.0 mA ≤ IO ≤ 1.0 A

∆IB———

———

—1.00.5

———

———

1.0—0.5

mA


RR— 59 — — 59 —

dB

Dropout Voltage (IO = 1.0 A, TJ = +25°C) ViI – VO — 2.0 — — 2.0 — Vdc


Vn— 10 — — 10 —

µV/VO

Output Resistance f = 1.0 kHz rO — 19 — — 19 — mΩShort Circuit Current Limit (TA = +25°C)

Vin = 35 VdcISC

— 0.2 — — 0.2 —A




MCT7824B MCT7824C


Output Voltage (TJ = +25°C) VO 23 24 25 23 24 25 Vdc

Output Voltage (5.0 mA ≤ IO ≤ 1.0 A, PO ≤15 W)27 Vdc ≤ Vin ≤ 38 Vdc28 Vdc ≤ Vin ≤ 38 Vdc

VO—

22.8—24

—25.2

22.8—

24—

25.2—

Vdc

Line Regulation, TJ = +25°C (Note 2)27 Vdc ≤ Vin ≤ 38 Vdc30 Vdc ≤ Vin ≤ 36 Vdc

Regline——

126.0

480240

——

126.0

480240

mV


Regload——

5.04.0

480240

——

5.04.0

480240

mV


Quiescent Current Change27 Vdc ≤ Vin ≤ 38 Vdc28 Vdc ≤ Vin ≤ 38 Vdc5.0 mA ≤ IO ≤ 1.0 A

∆IB———

———

—1.00.5

———

———

1.0—0.5

mA


RR— 56 — — 56 —

dB



Vn— 10 — — 10 —

µV/VO

Output Resistance f = 1.0 kHz rO — 20 — — 20 — mΩShort Circuit Current Limit (TA = +25°C)

Vin = 35 VdcISC

— 0.2 — — 0.2 —A


Average Temperature Coefficient of Output Voltage TCVO — –1.5 — — –1.5 — mV/°CNOTES: 1. Tlow = 0°C for MCT78XXC Thigh = +125°C for MCT78XXB, C. When the junction temperature exceeds +125°C, internal current limiting = – 40°C for MCT78XXB will reduce the output current to less than 1.0 A at a VI–VO of 15 V or



MCT7800

MCT78008

MOTOROLA

Figure 1. Peak Output Current as a Function ofInput-Output Differential Voltage

Figure 2. Ripple Rejection as a Function ofOutput Voltages (MCT78XXC)

Figure 3. Ripple Rejection as a Function ofFrequency (MCT78XXC)

Figure 4. Output Impedance as a Function ofOutput Voltage (MCT78XXC)

Figure 5. Quiescent Current as aFunction of Temperature

I O

VI – VO, INPUT-OUPUT VOLTAGE DIFFERENTIAL (V)

4.0

3.0

2.0

1.0

00 10 20 30 40

, OU

TPU

T C

UR

REN

T (A

)

TJ = – 40°C

TJ = +125°C

TJ = +25°C

80

70

60

50

404.0 6.0 8.0 10 12 14 16 18 20 22 24

VO, OUTPUT VOLTAGE (V)

RR

, RIP

PLE

REJ

ECTI

ON

(dB) f = 120 Hz

IO = 20 mA∆Vin = 1.0 Vrms

80

60

40

20

RR

, RIP

PLE

REJ

ECTI

ON

(dB)

100 1.0 k 10 k 100 kf, FREQUENCY (Hz)

10

Vin = 10 VVO = 5.0 VIO = 20 mA

f = 120 HzIO = 500 mACL = 0 µF

, OU

TPU

T IM

PED

ANC

E (m

)O

Ω

1000

500

300200

100

50

3020

104.0 8.0 12 16 20 24

VO, OUTPUT VOLTAGE (V)

Z

, QU

IESC

ENT

CU

RR

ENT

(mA)

B

6.0

4.0

3.0

2.0

1.0

0–75 – 50

TJ, JUNCTION TEMPERATURE (°C)– 25 0 25 50 75 100 125

I

Vin = 10 VVO = 5.0 VIO = 20 mA

MCT7805C 10 VMCT7812C 19 VMCT7815C 23 V

VinDevice

MCT7800

9MCT7800MOTOROLA

APPLICATIONS INFORMATION

Design ConsiderationsThe MCT7800 Series of fixed voltage regulators are

designed with thermal overload protection that shuts downthe circuit when subjected to an excessive power overloadcondition, internal short circuit protection that limits themaximum current the circuit will pass, and output transistorsafe-area compensation that reduces the output short circuitcurrent as the voltage across the pass transistor is increased.

In many low current applications, compensation capacitorsare not required. However, it is recommended that theregulator input be bypassed with a capacitor if the regulator isconnected to the power supply filter with long wire lengths, or

if the output load capacitance is large. An input bypasscapacitor should be selected to provide good high frequencycharacteristics to insure stable operation under all loadconditions. A 0.33 µF or larger tantalum, mylar, or othercapacitor having low internal impedance at high frequencies,should be chosen. The bypass capacitor should be mountedwith the shortest possible leads directly across the regulators’input terminals. Normally, good construction techniquesshould be used to minimize ground loops and lead resistancedrops since the regulator has no external sense lead.

Figure 6. Worst Case Power Dissipation versusAmbient Temperature (Case 221A)

Figure 7. Input Output Differential as aFunction of Junction Temperature

, PO

WER

DIS

SIPA

TIO

N (W

)D

20

16

12

8.0

4.0

0– 50 – 25 0 25 50 75 100 125 150

TA, AMBIENT TEMPERATURE (°C)

P No Heatsink

θHS = 0°C/W

θJC = 5°C/WθJA = 65°C/WTJ(max) = +150°C

DIF

FER

ENTI

AL (V

)I

O, I

NPU

T-O

UTP

UT

VOLT

AGE

2.5

2.0

1.5

1.0

–75 – 50 – 25 0 25 50 75 100 125TJ, JUNCTION TEMPERATURE (°C)

– V

V

IO = 1.0 A

200 mA 500 mA

0 mA

20 mA

0

0.5

θHS = 15°C/W

θHS = 5°C/W

∆VO = 2% of VO– – – Extended Curve for MCT78XXB

Figure 8. D 2PAK Thermal Resistance and MaximumPower Dissipation versus P.C.B. Copper Length

R, T

HER

MAL

RES

ISTA

NC

EJA θ JU

NC

TIO

N-T

O-A

IR (

C/W

)°

30

40

50

60

70

80

1.0

1.5

2.0

2.5

3.0

3.5

0 10 20 3025155.0

L, LENGTH OF COPPER (mm)

PD(max) for TA = 50°C

MinimumSize Pad

2.0 oz. CopperL

L

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

Free AirMountedVertically

P D, M

AXIM

UM

PO

WER

DIS

SIPA

TIO

N (W

)

RθJA

DEFINITIONS

Line Regulation — The change in output voltage for achange in the input voltage. The measurement is made underconditions of low dissipation or by using pulse techniquessuch that the average chip temperature is not significantlyaffected.

Load Regulation — The change in output voltage for achange in load current at constant chip temperature.

Maximum Power Dissipation — The maximum totaldevice dissipation for which the regulator will operate withinspecifications.

Quiescent Current — That part of the input current that isnot delivered to the load.

Output Noise Voltage — The rms AC voltage at theoutput, with constant load and no input ripple, measured overa specified frequency range.

Long Term Stability — Output voltage stability underaccelerated life test conditions with the maximum ratedvoltage listed in the devices’ electrical characteristics andmaximum power dissipation.

MCT7800

MCT780010

MOTOROLA

T SUFFIXPLASTIC PACKAGE

CASE 221A-06

OUTLINE DIMENSIONS

MIN MINMAX MAXINCHES MILLIMETERS

DIMABCDFGHJKLNQRSTUVZ

14.489.664.070.643.612.422.800.46

12.701.154.832.542.041.155.970.001.15—

15.7510.28

4.820.883.732.663.930.64

14.271.525.333.042.791.396.471.27—

2.04

0.5700.3800.1600.0250.1420.0950.1100.0180.5000.0450.1900.1000.0800.0450.2350.0000.045

—

0.6200.4050.1900.0350.1470.1050.1550.0250.5620.0600.2100.1200.1100.0550.2550.050

— 0.080

NOTES:1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.2. CONTROLLING DIMENSION: INCH.3. DIM Z DEFINES A ZONE WHERE ALL BODY AND

LEAD IRREGULARITIES ARE ALLOWED.

-T- SEATINGPLANE

CST

U

J

R

FB

Q

H

Z

L

V

G

ND

K

A4

1 2 3

D2T SUFFIXPLASTIC PACKAGE

CASE 936-03(D2PAK)

5 REF5 REF

A

1 2 3

K

F

B

J

S

H

0.010 (0.254) TM

D

G

C

E

-T-

ML

P

NR

V

U

TERMINAL 4NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSIY14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.3. TAB CONTOUR OPTIONAL WITHIN DIMENSIONS

A AND K.4. DIMENSIONS U AND V ESTABLISH A MINIMUM

MOUNTING SURFACE FOR TERMINAL 4.5. DIMENSIONS A AND B DO NOT INCLUDE MOLD

FLASH OR GATE PROTRUSIONS. MOLD FLASHAND GATE PROTRUSIONS NOT TO EXCEED0.025 (0.635) MAXIMUM.

DIMA

MIN MAX MIN MAXMILLIMETERS

0.386 0.403 9.804 10.236

INCHES

B 0.356 0.368 9.042 9.347C 0.170 0.180 4.318 4.572D 0.026 0.036 0.660 0.914E 0.045 0.055 1.143 1.397F 0.051 REF 1.295 REFG 0.100 BSC 2.540 BSCH 0.539 0.579 13.691 14.707J 0.125 MAX 3.175 MAXK 0.050 REF 1.270 REFL 0.000 0.010 0.000 0.254M 0.088 0.102 2.235 2.591N 0.018 0.026 0.457 0.660P 0.058 0.078 1.473 1.981RS 0.116 REF 2.946 REFU 0.200 MIN 5.080 MINV 0.250 MIN 6.350 MIN

OPTIONALCHAMFER

MCT7800

11MCT7800MOTOROLA

NOTES

MCT7800

MCT780012

MOTOROLA

Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regardingthe suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit,and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters can and do vary in differentapplications. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. Motorola doesnot convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components insystems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure ofthe Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any suchunintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmlessagainst all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or deathassociated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part.Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.

Literature Distribution Centers:USA: Motorola Literature Distribution; P.O. Box 20912; Phoenix, Arizona 85036.EUROPE: Motorola Ltd.; European Literature Centre; 88 Tanners Drive, Blakelands, Milton Keynes, MK14 5BP, England.JAPAN: Nippon Motorola Ltd.; 4-32-1, Nishi-Gotanda, Shinagawa-ku, Tokyo 141, Japan.ASIA PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Center, No. 2 Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong.

MCT7800/D

◊ 1PHX33530-3 PRINTED IN USA (8/94) MPS/POD LINEAR YCAAAA

DATA SHEET

Product specificationFile under Discrete Semiconductors, SC13b

April 1995

DISCRETE SEMICONDUCTORS

BS250P-channel enhancement modevertical D-MOS transistor

April 1995 2

Philips Semiconductors Product specification

P-channel enhancement mode verticalD-MOS transistor

BS250

DESCRIPTION

P-channel enhancement modevertical D-MOS transistor in TO-92variant envelope and intended for usein relay, high-speed andline-transformer drivers.

FEATURES

• Low RDS(on)

• Direct interface to C-MOS

• High-speed switching

• No second breakdown

PINNING - TO-92 VARIANT

1 = source

2 = gate

3 = drain

QUICK REFERENCE DATA

Drain-source voltage −VDS max. 45 V

Gate-source voltage (open drain) ±VGSO max. 20 V

Drain current (DC) −ID max. 0.25 A

Total power dissipation

up to Tamb = 25 °C Ptot max. 0.83 W

Drain-source ON-resistancetyp.max.

914

ΩΩ−ID = 200 mA; −VGS = 10 V RDS(on)

Transfer admittance

−ID = 200 mA; −VDS = 15 V Yfs typ. 125 mS

PIN CONFIGURATION

Fig.1 Simplified outline and symbol.

Note: Various pinout configurations available.

handbook, halfpage

1

32

MAM147 s

d

g

April 1995 3



BS250

RATINGSLimiting values in accordance with the Absolute Maximum System (IEC 134)

THERMAL RESISTANCE

Note

1. Transistor mounted on printed-circuit board, max. lead length 4 mm.

CHARACTERISTICSTj = 25 °C unless otherwise specified

Drain-source voltage −VDS max. 45 V

Gate-source voltage (open drain) ± VGSO max. 20 V

Drain current (DC) −ID max. 0.25 A

Drain current (peak value) −IDM max. 0.5 A

Total power dissipation up to Tamb = 25 °C (note 1) Ptot max. 0.83 W

Storage temperature range Tstg −65 to + 150 °CJunction temperature Tj max. 150 °C

From junction to ambient (note 1) Rth j-a = 150 K/W

Drain-source breakdown voltage

− ID = 100 µA; VGS = 0 −V(BR)DSS min. 45 V

Drain-source leakage current

−VDS = 25 V; VGS = 0 −IDSS max. 0.5 µA

Gate-source leakage current

−VGS = 15 V; VDS = 0 −IGSS max. 20 nA

Gate threshold voltagemin.max.

1.03.5

VV

−ID = 1 mA; VDS = VGS −VGS(th)

Drain-source ON-resistancetyp.max.

914

ΩΩ−ID = 200 mA; −VGS = 10 V RDS(on)

Transfer admittance

−ID = 200 mA; −VDS = 15 V Yfs typ. 125 mS

Input capacitance at f = 1 MHztyp.max.

3045

pFpF

−VDS = 10 V; VGS = 0 Ciss

Output capacitance at f = 1 MHztyp.max.

2030

pFpF

−VDS = 10 V; VGS = 0 Coss

Feedback capacitance at f = 1 MHztyp.max.

510

pFpF

−VDS = 10 V; VGS = 0 Crss

April 1995 4



BS250

Switching times (see Figs 2 and 3)tontoff

typ.typ.

410

nsns

−ID = 200 mA; −VDD = 40 V; −VGS = 0 to 10 V

Fig.2 Switching times test circuit. Fig.3 Input and output waveforms.

April 1995 5



BS250

PACKAGE OUTLINES

UNIT A

REFERENCESOUTLINEVERSION

EUROPEANPROJECTION ISSUE DATE

IEC JEDEC EIAJ

mm5.25.0

b

0.480.40

c

0.450.40

D

4.84.4

d

1.71.4

E

4.23.6

L

14.512.7

e

2.54

e1

1.27

L1(1)

maxL2

max

2.5 2.5

b1

0.660.56

DIMENSIONS (mm are the original dimensions)

Notes

1. Terminal dimensions within this zone are uncontrolled to allow for flow of plastic and terminal irregularities.

SOT54 variant TO-92 SC-43

A L

0 2.5 5 mm

scale

b

c

D

b1 L1

d

E

Plastic single-ended leaded (through hole) package; 3 leads (on-circle) SOT54 variant

1

2

3

L2

e1e

97-04-14

April 1995 6



BS250

DEFINITIONS

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of theseproducts can reasonably be expected to result in personal injury. Philips customers using or selling these products foruse in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from suchimproper use or sale.

Data sheet status

Objective specification This data sheet contains target or goal specifications for product development.

Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.

Product specification This data sheet contains final product specifications.

Application information

Where application information is given, it is advisory and does not form part of the specification.

April 1995 7



BS250

NOTES

Internet: http://www.semiconductors.philips.com

Philips Semiconductors – a worldwide company

© Philips Electronics N.V. 1997 SCA54

All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changedwithout notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any licenseunder patent- or other industrial or intellectual property rights.

Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB,Tel. +31 40 27 82785, Fax. +31 40 27 88399

New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND,Tel. +64 9 849 4160, Fax. +64 9 849 7811

Norway: Box 1, Manglerud 0612, OSLO,Tel. +47 22 74 8000, Fax. +47 22 74 8341

Philippines: Philips Semiconductors Philippines Inc.,106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI,Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474

Poland: Ul. Lukiska 10, PL 04-123 WARSZAWA,Tel. +48 22 612 2831, Fax. +48 22 612 2327

Portugal: see Spain

Romania: see Italy

Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW,Tel. +7 095 755 6918, Fax. +7 095 755 6919

Singapore: Lorong 1, Toa Payoh, SINGAPORE 1231,Tel. +65 350 2538, Fax. +65 251 6500

Slovakia: see Austria

Slovenia: see Italy

South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale,2092 JOHANNESBURG, P.O. Box 7430 Johannesburg 2000,Tel. +27 11 470 5911, Fax. +27 11 470 5494

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Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH,Tel. +41 1 488 2686, Fax. +41 1 481 7730

Taiwan: Philips Semiconductors, 6F, No. 96, Chien Kuo N. Rd., Sec. 1,TAIPEI, Taiwan Tel. +886 2 2134 2865, Fax. +886 2 2134 2874

Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd.,209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260,Tel. +66 2 745 4090, Fax. +66 2 398 0793

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Ukraine : PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7,252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461

United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes,MIDDLESEX UB3 5BX, Tel. +44 181 730 5000, Fax. +44 181 754 8421

United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409,Tel. +1 800 234 7381

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Vietnam: see Singapore

Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,Tel. +381 11 625 344, Fax.+381 11 635 777

For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications,Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825

Argentina: see South America

Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113,Tel. +61 2 9805 4455, Fax. +61 2 9805 4466

Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213,Tel. +43 1 60 101, Fax. +43 1 60 101 1210

Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6,220050 MINSK, Tel. +375 172 200 733, Fax. +375 172 200 773

Belgium: see The Netherlands

Brazil: see South America

Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor,51 James Bourchier Blvd., 1407 SOFIA,Tel. +359 2 689 211, Fax. +359 2 689 102

Canada: PHILIPS SEMICONDUCTORS/COMPONENTS,Tel. +1 800 234 7381

China/Hong Kong: 501 Hong Kong Industrial Technology Centre,72 Tat Chee Avenue, Kowloon Tong, HONG KONG,Tel. +852 2319 7888, Fax. +852 2319 7700

Colombia: see South America

Czech Republic: see Austria

Denmark: Prags Boulevard 80, PB 1919, DK-2300 COPENHAGEN S,Tel. +45 32 88 2636, Fax. +45 31 57 0044

Finland: Sinikalliontie 3, FIN-02630 ESPOO,Tel. +358 9 615800, Fax. +358 9 61580920

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Germany: Hammerbrookstraße 69, D-20097 HAMBURG,Tel. +49 40 23 53 60, Fax. +49 40 23 536 300

Greece: No. 15, 25th March Street, GR 17778 TAVROS/ATHENS,Tel. +30 1 4894 339/239, Fax. +30 1 4814 240

Hungary: see Austria

India: Philips INDIA Ltd, Shivsagar Estate, A Block, Dr. Annie Besant Rd.Worli, MUMBAI 400 018, Tel. +91 22 4938 541, Fax. +91 22 4938 722

Indonesia: see Singapore

Ireland: Newstead, Clonskeagh, DUBLIN 14,Tel. +353 1 7640 000, Fax. +353 1 7640 200

Israel: RAPAC Electronics, 7 Kehilat Saloniki St, PO Box 18053,TEL AVIV 61180, Tel. +972 3 645 0444, Fax. +972 3 649 1007

Italy: PHILIPS SEMICONDUCTORS, Piazza IV Novembre 3,20124 MILANO, Tel. +39 2 6752 2531, Fax. +39 2 6752 2557

Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku, TOKYO 108,Tel. +81 3 3740 5130, Fax. +81 3 3740 5077

Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL,Tel. +82 2 709 1412, Fax. +82 2 709 1415

Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR,Tel. +60 3 750 5214, Fax. +60 3 757 4880

Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905,Tel. +9-5 800 234 7381

Middle East: see Italy

Printed in The Netherlands 137107/00/01/pp8 Date of release: April 1995 Document order number: 9397 750 02458

TELEFUNKEN SemiconductorsBZX85C...

1Rev. A1: 12.12.1994

Silicon Epitaxial Planar Z–Diodes

Features

Sharp edge in reverse characteristics

Low reverse current

Low noise

Very high stability

Available with tighter tolerances

Applications

Voltage stabilization94 9369

Absolute Maximum RatingsTj = 25C

Parameter Test Conditions Type Symbol Value Unit

Power dissipation l=4mm, TL=25C PV 1.3 W

Junction temperature Tj 175 C

Storage temperature range Tstg –65...+175 C

Maximum Thermal ResistanceTj = 25C

Parameter Test Conditions Symbol Value Unit

Junction ambient l=4mm, TL=constant RthJA 110 K/W

CharacteristicsTj = 25C

Parameter Test Conditions Type Symbol Min Typ Max Unit

Forward voltage IF=200mA VF 1 V


2 Rev. A1: 12.12.1994

Type VZnorm IZT for VZT 1) and rzjT rzjk at IZK IR at VR TKVZ

BZX85C... V mA V mA A V %/K

2V7 2.7 80 2.5 to 2.9 < 20 < 400 1 < 150 1 –0.08 to –0.05

3V0 3.0 80 2.8 to 3.2 < 20 < 400 1 < 100 1 –0.08 to –0.05

3V3 3.3 80 3.1 to 3.5 < 20 < 400 1 < 40 1 –0.08 to –0.05

3V6 3.6 60 3.4 to 3.8 < 20 < 500 1 < 20 1 –0.08 to –0.05

3V9 3.9 60 3.7 to 4.1 < 15 < 500 1 < 10 1 –0.07 to –0.02

4V3 4.3 50 4.0 to 4.6 < 13 < 500 1 < 3 1 –0.07 to –0.01

4V7 4.7 45 4.4 to 5.0 < 13 < 600 1 < 3 1 –0.03 to +0.04

5V1 5.1 45 4.8 to 5.4 < 10 < 500 1 < 1 1.5 –0.01 to +0.04

5V6 5.6 45 5.2 to 6.0 < 7 < 400 1 < 1 2 0 to +0.045

6V2 6.2 35 5.8 to 6.6 < 4 < 300 1 < 1 3 +0.01 to +0.055

6V8 6.8 35 6.4 to 7.2 < 3.5 < 300 1 < 1 4 +0.015 to +0.06

7V5 7.5 35 7.0 to 7.9 < 3 < 200 0.5 < 1 4.5 +0.02 to +0.065

8V2 8.2 25 7.7 to 8.7 < 5 < 200 0.5 < 1 6.2 0.03 to 0.07

9V1 9.1 25 8.5 to 9.6 < 5 < 200 0.5 < 1 6.8 0.035 to 0.075

10 10 25 9.4 to 10.6 < 7 < 200 0.5 < 0.5 7 0.04 to 0.08

11 11 20 10.4 to 11.6 < 8 < 300 0.5 < 0.5 8.2 0.045 to 0.08

12 12 20 11.4 to 12.7 < 9 < 350 0.5 < 0.5 9.1 0.045 to 0.085

13 13 20 12.4 to 14.1 < 10 < 400 0.5 < 0.5 10 0.05 to 0.085

15 15 15 13.8 to 15.6 < 15 < 500 0.5 < 0.5 11 0.055 to 0.09

16 16 15 15.3 to 17.1 < 15 < 500 0.5 < 0.5 12 0.055 to 0.09

18 18 15 16.8 to 19.1 < 20 < 500 0.5 < 0.5 13 0.06 to 0.09

20 20 10 18.8 to 21.2 < 24 < 600 0.5 < 0.5 15 0.06 to 0.09

22 22 10 20.8 to 23.3 < 25 < 600 0.5 < 0.5 16 0.06 to 0.095

24 24 10 22.8 to 25.6 < 25 < 600 0.5 < 0.5 18 0.06 to 0.095

27 27 8 25.1 to 28.9 < 30 < 750 0.25 < 0.5 20 0.06 to 0.095

30 30 8 28 to 32 < 30 < 1000 0.25 < 0.5 22 0.06 to 0.095

33 33 8 31 to 35 < 35 < 1000 0.25 < 0.5 24 0.06 to 0.095

36 36 8 34 to 38 < 40 < 1000 0.25 < 0.5 27 0.06 to 0.095

39 39 6 37 to 41 < 50 < 1000 0.25 < 0.5 30 0.06 to 0.095

43 43 6 40 to 46 < 50 < 1000 0.25 < 0.5 33 0.06 to 0.095

47 47 4 44 to 50 < 90 < 1500 0.25 < 0.5 36 0.06 to 0.095

51 51 4 48 to 54 < 115 < 1500 0.25 < 0.5 39 0.06 to 0.095

56 56 4 52 to 60 < 120 < 2000 0.25 < 0.5 43 0.06 to 0.095

62 62 4 58 to 66 < 125 < 2000 0.25 < 0.5 47 0.06 to 0.095

68 68 4 64 to 72 < 130 < 2000 0.25 < 0.5 51 0.06 to 0.095

75 75 4 70 to 79 < 135 < 2000 0.25 < 0.5 56 0.06 to 0.095

1) Tighter tolerances available on request.


3Rev. A1: 12.12.1994

Typical Characteristics (Tj = 25C unless otherwise specified)

–500

0.4

0.8

1.2

1.6

2.0

95 9612

0 50 100 150

P

– T

otal

Pow

er D

issi

patio

n (

W )

tot

Tamb – Ambient Temperature ( °C )

200

l=4mm

l=10mml=20mm

Figure 1 : Total Power Dissipation vs. Ambient Temperature

0 10 20 30 401

10

100

1000

60

95 9616

C

– D

iode

Cap

acita

nce

( pF

)D

VZ – Z-Voltage ( V )

50

f=1MHzTamb=25°C

VR=30VVR=20VVR=5VVR=2VVR=0V

Figure 3 : Diode Capacitance vs. Z–Voltage

0 5 10 15 200

50

100

150

200

250

30

95 9613

R

–

The

rm. R

esis

t. Ju

nctio

n / A

mbi

ent (

K/W

)th

JA

l – Lead Length ( mm )

25

l l

TL=constant

Figure 2 : Thermal Resistance vs. Lead Length

1 10 100

95 9615

1

10

100

1000r

– D

iffer

entia

l Z-R

esis

tanc

e (

)

Z

VZ – Z-Voltage ( V )

IZ=1mA

5mA

10mA

2mA

20mA

Figure 4 : Differential Z–Resistance vs. Z–Voltage

1

10

100

1000

Z

– T

herm

al R

esis

tanc

e fo

r P

ulse

Con

d. (

K/W

)th

p

tp – Pulse Length ( ms )95 9614

10–1 100 101 102 103

tp/T=0.5

tp/T=0.2

tp/T=0.1

tp/T=0.05

tp/T=0.02tp/T=0.01

Single Pulse

RthJA=110K/WT=Tjmax–Tamb

iZM=(–VZ+(VZ2+4rzjT/Zthp)1/2)/(2rzj)

Figure 5 : Thermal Response


4 Rev. A1: 12.12.1994

Dimensions in mmCathode Identification

∅ 2.5 max.

∅ 0.85 max.

4.1 max.26 min.94 9368

technical drawingsaccording to DINspecifications

Standard Glass Case54 B 2 DIN 41880JEDEC DO 41Weight max. 0.3g 26 min.


5Rev. A1: 12.12.1994

OZONE DEPLETING SUBSTANCES POLICY STATEMENT

It is the policy of TEMIC TELEFUNKEN microelectronic GmbH to

1. Meet all present and future national and international statutory requirements and

2. Regularly and continuously improve the performance of our products, processes, distribution and operating systemswith respect to their impact on the health and safety of our employees and the public, as well as their impact on theenvironment.

Of particular concern is the control or elimination of releases into the atmosphere of those substances which are knownas ozone depleting substances (ODSs).

The Montreal Protocol (1987) and its London Amendments (1990) will soon severely restrict the use of ODSs and forbidtheir use within the next ten years. Various national and international initiatives are pressing for an earlier ban on thesesubstances.

TEMIC TELEFUNKEN microelectronic GmbH semiconductor division has been able to use its policy of continuousimprovements to eliminate the use of any ODSs listed in the following documents.

1. Annex A, B and list of transitional substances of the Montreal Protocol and the London Amendments respectively

2. Class I and II ozone depleting substances in the Clean Air Act Amendments of 1990 by the Environmental ProtectionAgency (EPA) in the USA and

3. Council Decision 88/540/EEC and 91/690/EEC Annex A, B and C ( transitional substances) respectively.

TEMIC can certify that our semiconductors are not manufactured with and do not contain ozone depleting substances.

We reserve the right to make changes to improve technical design without further notice.Parameters can vary in different applications. All operating parameters must be validated for each customer

application by the customer. Should the buyer use TEMIC products for any unintended or unauthorized application,the buyer shall indemnify TEMIC against all claims, costs, damages, and expenses, arising out of, directly or

indirectly, any claim of personal damage, injury or death associated with such unintended or unauthorized use.

TEMIC TELEFUNKEN microelectronic GmbH, P.O.B. 3535, D-74025 Heilbronn, GermanyTelephone: 49 (0)7131 67 2831, Fax Number: 49 (0)7131 67 2423

TL/F/5982

CD

4093B

M/C

D4093B

CQ

uad

2-In

putN

AN

DSchm

ittTrig

ger

February 1993

CD4093BM/CD4093BC Quad2-Input NAND Schmitt Trigger

General DescriptionThe CD4093B consists of four Schmitt-trigger circuits. Each

circuit functions as a 2-input NAND gate with Schmitt-trigger

action on both inputs. The gate switches at different points

for positive and negative-going signals. The difference be-

tween the positive (VTa) and the negative voltage (VT

b) is

defined as hysteresis voltage (VH).

All outputs have equal source and sink currents and con-

form to standard B-series output drive (see Static Electrical

Characteristics).

FeaturesY Wide supply voltage range 3.0V to 15VY Schmitt-trigger on each input

with no external componentsY Noise immunity greater than 50%

Y Equal source and sink currentsY No limit on input rise and fall timeY Standard B-series output driveY Hysteresis voltage (any input) TA e 25§C

Typical VDD e 5.0V VH e 1.5V

VDD e 10V VH e 2.2V

VDD e 15V VH e 2.7V

Guaranteed VH e 0.1 VDD

ApplicationsY Wave and pulse shapersY High-noise-environment systemsY Monostable multivibratorsY Astable multivibratorsY NAND logic

Connection Diagram

Dual-In-Line Package

TL/F/5982–1

Top View

Order Number CD4093B

C1995 National Semiconductor Corporation RRD-B30M105/Printed in U. S. A.

Absolute Maximum Ratings (Notes 1 & 2)

If Military/Aerospace specified devices are required,

please contact the National Semiconductor Sales

Office/Distributors for availability and specifications.

DC Supply Voltage (VDD) b0.5 to a18 VDC

Input Voltage (VIN) b0.5 to VDD a0.5 VDC

Storage Temperature Range (TS) b65§C to a150§CPower Dissipation (PD)

Dual-In-Line 700 mW

Small Outline 500 mW

Lead Temperature (TL)

(Soldering, 10 seconds) 260§C

Recommended OperatingConditions (Note 2)

DC Supply Voltage (VDD) 3 to 15 VDC

Input Voltage (VIN) 0 to VDD VDC

Operating Temperature Range (TA)

CD4093BM b55§C to a125§CCD4093BC b40§C to a85§C

DC Electrical Characteristics CD4093BM (Note 2)

Symbol Parameter Conditionsb55§C a25§C a125§C

UnitsMin Max Min Typ Max Min Max

IDD Quiescent Device VDD e 5V 0.25 0.25 7.5 mA

Current VDD e 10V 0.5 0.5 15.0 mA

VDD e 15V 1.0 1.0 30.0 mA

VOL Low Level VIN e VDD, lIOl k 1 mA

Output Voltage VDD e 5V 0.05 0 0.05 0.05 V

VDD e 10V 0.05 0 0.05 0.05 V

VDD e 15V 0.05 0 0.05 0.05 V

VOH High Level VIN e VSS, lIOl k 1 mA

Output Voltage VDD e 5V 4.95 4.95 5 4.95 V

VDD e 10V 9.95 9.95 10 9.95 V

VDD e 15V 14.95 14.95 15 14.95 V

VTb Negative-Going Threshold lIOl k 1 mA

Voltage (Any Input) VDD e 5V, VO e 4.5V 1.3 2.25 1.5 1.8 2.25 1.5 2.3 V

VDD e 10V, VO e 9V 2.85 4.5 3.0 4.1 4.5 3.0 4.65 V

VDD e 15V, VO e 13.5V 4.35 6.75 4.5 6.3 6.75 4.5 6.9 V

VTa Positive-Going Threshold lIOl k 1 mA


VDD e 10V, VO e 1V 5.5 7.15 5.5 6.2 7.0 5.35 7.0 V

VDD e 15V, VO e 1.5V 8.25 10.65 8.25 9.0 10.5 8.1 10.5 V

VH Hysteresis (VTa b VT

b) VDD e 5V 0.5 2.35 0.5 1.5 2.0 0.35 2.0 V

(Any Input) VDD e 10V 1.0 4.30 1.0 2.2 4.0 0.70 4.0 V

VDD e 15V 1.5 6.30 1.5 2.7 6.0 1.20 6.0 V

IOL Low Level Output VIN e VDD

Current (Note 3) VDD e 5V, VO e 0.4V 0.64 0.51 0.88 0.36 mA

VDD e 10V, VO e 0.5V 1.6 1.3 2.25 0.9 mA

VDD e 15V, VO e 1.5V 4.2 3.4 8.8 2.4 mA

IOH High Level Output VIN e VSS

Current (Note 3) VDD e 5V, VO e 4.6V b0.64 0.51 b0.88 b0.36 mA

VDD e 10V, VO e 9.5V b1.6 b1.3 b2.25 b0.9 mA


IIN Input Current VDD e 15V, VIN e 0V b0.1 b10b5 b0.1 b1.0 mA

VDD e 15V, VIN e 15V 0.1 10b5 0.1 1.0 mA

Note 1: ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed; they are not meant to imply that the devices

should be operated at these limits. The table of ‘‘Recommended Operating Conditions’’ and ‘‘Electrical Characteristics’’ provides conditions for actual device

operation.

Note 2: VSS e 0V unless otherwise specified.

Note 3: IOH and IOL are tested one output at a time.

2

DC Electrical Characteristics CD4093BC (Note 2)

Symbol Parameter Conditionsb40§C a25§C a85§C

UnitsMin Max Min Typ Max Min Max

IDD Quiescent Device VDD e 5V 1.0 1.0 7.5 mA

Current VDD e 10V 2.0 2.0 15.0 mA

VDD e 15V 4.0 4.0 30.0 mA

VOL Low Level VIN e VDD, lIOl k 1 mA

Output Voltage VDD e 5V 0.05 0 0.05 0.05 V

VDD e 10V 0.05 0 0.05 0.05 V

VDD e 15V 0.05 0 0.05 0.05 V

VOH High Level VIN e VSS, lIOl k 1 mA

Output Voltage VDD e 5V 4.95 4.95 5 4.95 V

VDD e 10V 9.95 9.95 10 9.95 V

VDD e 15V 14.95 14.95 15 14.95 V

VTb Negative-Going Threshold lIOl k 1 mA


VDD e 10V, VO e 9V 2.85 4.5 3.0 4.1 4.5 3.0 4.65 V

VDD e 15V, VO e 13.5V 4.35 6.75 4.5 6.3 6.75 4.5 6.9 V

VTa Positive-Going Threshold lIOl k 1 mA


VDD e 10V, VO e 1V 5.5 7.15 5.5 6.2 7.0 5.35 7.0 V

VDD e 15V, VO e 1.5V 8.25 10.65 8.25 9.0 10.5 8.1 10.5 V

VH Hysteresis (VTa b VT

b) VDD e 5V 0.5 2.35 0.5 1.5 2.0 0.35 2.0 V

(Any Input) VDD e 10V 1.0 4.3 1.0 2.2 4.0 0.70 4.0 V

VDD e 15V 1.5 6.3 1.5 2.7 6.0 1.20 6.0 V

IOL Low Level Output VIN e VDD

Current (Note 3) VDD e 5V, VO e 0.4V 0.52 0.44 0.88 0.36 mA

VDD e 10V, VO e 0.5V 1.3 1.1 2.25 0.9 mA

VDD e 15V, VO e 1.5V 3.6 3.0 8.8 2.4 mA

IOH High Level Output VIN e VSS

Current (Note 3) VDD e 5V, VO e 4.6V b0.52 0.44 b0.88 b0.36 mA



IIN Input Current VDD e 15V, VIN e 0V b0.3 b10b5 b0.3 b1.0 mA

VDD e 15V, VIN e 15V 0.3 10b5 0.3 1.0 mA

AC Electrical Characteristics*TA e 25§C, CL e 50 pF, RL e 200k, Input tr, tf e 20 ns, unless otherwise specified

Symbol Parameter Conditions Min Typ Max Units

tPHL, tPLH Propagation Delay Time VDD e 5V 300 450 ns

VDD e 10V 120 210 ns

VDD e 15V 80 160 ns

tTHL, tTLH Transition Time VDD e 5V 90 145 ns

VDD e 10V 50 75 ns

VDD e 15V 40 60 ns

CIN Input Capacitance (Any Input) 5.0 7.5 pF

CPD Power Dissipation Capacitance (Per Gate) 24 pF

*AC Parameters are guaranteed by DC correlated testing.

Note 2: VSS e 0V unless otherwise specified.

Note 3: IOH and IOL are tested one output at a time.

3

Typical ApplicationsGated Oscillator

TL/F/5982–2

Assume t1 a t2 ll tPHL a tPLH then:

t0 e RC fin [VDD/VTb]

t1 e RC fin [(VDD b VTb)/(VDD b VT

a)]

t2 e RC fin [VTa/V

Tb]

f e

1

t1 a t2e

1

RC fin(VT

a) (VDD b VTb)

(VTb)(VDD b VT

a)

TL/F/5982–3

Gated One-Shot

TL/F/5982–4

TL/F/5982–5

(a) Negative-Edge Triggered

TL/F/5982–6

TL/F/5982–7

(b) Positive-Edge Triggered

4

Typical Performance Characteristics

Typical Transfer

Characteristics

TL/F/5982–8

Guaranteed Hysteresis vs VDD

TL/F/5982–9

Guaranteed Trigger Threshold

Voltage vs VDD

TL/F/5982–10

Guaranteed Hysteresis vs VDD

TL/F/5982–11

Input and Output Characteristics

TL/F/5982–12

Output Characteristic Input Characteristic

TL/F/5982–13

VNML e VIH(MIN) b VOL j VIH(MIN) e VTa

(MIN)

VNMH e VOH b VIL(MAX) j VDD b VIL(MAX) e VDD b VTb

(MAX)

AC Test Circuits and Switching Time Waveforms

TL/F/5982–14

TL/F/5982–15

5

CD

4093B

M/C

D4093B

CQ

uad

2-InputN

AN

DSchm

ittTrigger

Physical Dimensions inches (millimeters)

Ceramic Dual-In-Line Package (J)

Order Number CD4093BMJ or CD4093BCJ

NS Package Number J14A

Molded Dual-In-Line Package (N)

Order Number CD4093BM or CD4093BCN

NS Package Number N14A

LIFE SUPPORT POLICY

NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT

DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL

SEMICONDUCTOR CORPORATION. As used herein:

1. Life support devices or systems are devices or 2. A critical component is any component of a life

systems which, (a) are intended for surgical implant support device or system whose failure to perform can

into the body, or (b) support or sustain life, and whose be reasonably expected to cause the failure of the life

failure to perform, when properly used in accordance support device or system, or to affect its safety or

with instructions for use provided in the labeling, can effectiveness.

be reasonably expected to result in a significant injury

to the user.

National Semiconductor National Semiconductor National Semiconductor National SemiconductorCorporation Europe Hong Kong Ltd. Japan Ltd.1111 West Bardin Road Fax: (a49) 0-180-530 85 86 13th Floor, Straight Block, Tel: 81-043-299-2309Arlington, TX 76017 Email: cnjwge@ tevm2.nsc.com Ocean Centre, 5 Canton Rd. Fax: 81-043-299-2408Tel: 1(800) 272-9959 Deutsch Tel: (a49) 0-180-530 85 85 Tsimshatsui, KowloonFax: 1(800) 737-7018 English Tel: (a49) 0-180-532 78 32 Hong Kong

Fran3ais Tel: (a49) 0-180-532 93 58 Tel: (852) 2737-1600Italiano Tel: (a49) 0-180-534 16 80 Fax: (852) 2736-9960

National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.

HN58C256A SeriesHN58C257A Series

256k EEPROM (32-kword × 8-bit)Ready/Busy and RES function (HN58C257A)

ADE-203-410D (Z)Rev. 4.0

Oct. 24, 1997

Description

The Hitachi HN58C256A and HN58C257A are electrically erasable and programmable ROMs organizedas 32768-word × 8-bit. They have realized high speed low power consumption and high reliability byemploying advanced MNOS memory technology and CMOS process and circuitry technology. They alsohave a 64-byte page programming function to make their write operations faster.

Features

• Single 5 V supply: 5 V ±10%

• Access time: 85 ns/100 ns (max)

• Power dissipation

Active: 20 mW/MHz, (typ)

Standby: 110 µW (max)

• On-chip latches: address, data, CE, OE, WE• Automatic byte write: 10 ms max

• Automatic page write (64 bytes): 10 ms max

• Ready/Busy (only the HN58C257A series)

• Data polling and Toggle bit

• Data protection circuit on power on/off

• Conforms to JEDEC byte-wide standard

• Reliable CMOS with MNOS cell technology

• 105 erase/write cycles (in page mode)

• 10 years data retention

• Software data protection

• Write protection by RES pin (only the HN58C257A series)

• Industrial versions (Temperature range: – 20 to 85˚C and – 40 to 85°C) are also available.

HN58C256A Series, HN58C257A Series

2

Ordering Information

Type No. Access time Package

HN58C256AP-85HN58C256AP-10

85 ns100 ns

600 mil 28-pin plastic DIP (DP-28)

HN58C256AFP-85HN58C256AFP-10

85 ns100 ns

400 mil 28-pin plastic SOP (FP-28D)

HN58C256AT-85HN58C256AT-10

85 ns100 ns

28-pin plastic TSOP (TFP-28DB)

HN58C257AT-85HN58C257AT-10

85 ns100 ns

8 × 14 mm2 32-pin plastic TSOP (TFP-32DA)

Pin Arrangement

HN58C256AP/AFP SeriesHN58C256AT Series

HN58C257AT Series

(Top view)

(Top view)

(Top view)

1234567891011121314

2827262524232221201918171615

A14A12A7A6A5A4A3A2A1A0

I/O0I/O1I/O2VSS

VCC

WEA13A8A9A11

OEA10

CEI/O7I/O6I/O5I/O4I/O3

A2A1A0

I/O0I/O1I/O2VSSI/O3I/O4I/O5I/O6I/O7CE

A10

A3A4A5A6A7A12A14VCCWEA13A8A9A11OE

1516171819202122232425262728

1413121110987654321

A2A1A0

I/O0I/O1I/O2VSSI/O3I/O4I/O5I/O6I/O7

CEA10

A3A4A5A6A7A12A14

VCC

WEA13A8A9A11OE

1718192021222324252627282930

161514131211109876543

3132

21

NC

NC

RES

RDY/Busy


3

Pin Description

Pin name Function

A0 to A14 Address input

I/O0 to I/O7 Data input/output

OE Output enable

CE Chip enable

WE Write enable

VCC Power supply

VSS Ground

RDY/Busy*1 Ready busy

RES*1 Reset

NC No connection

Note: 1. This function is supported by only the HN58C257A series.

Block Diagram

Note: This function is supported by only the HN58C257A series.

V

V

OE

CE

A5

A0

A6

A14

WE

CC

SS

I/O0 I/O7High voltage generator

Control logic and timing

Y decoder

X decoder

Address

buffer and

latch

I/O bufferandinput latch

Y gating

Memory array

Data latch

RES

RDY/Busy

RES

*1

*1

*1

to

to

to


4

Operation Table

Operation CE OE WE RES*3 RDY/Busy*3 I/O

Read VIL VIL VIH VH*1 High-Z Dout

Standby VIH ×*2 × × High-Z High-Z

Write VIL VIH VIL VH High-Z to VOL Din

Deselect VIL VIH VIH VH High-Z High-Z

Write inhibit × × VIH × — —

× VIL × × — —

Data polling VIL VIL VIH VH VOL Dout (I/O7)

Program reset × × × VIL High-Z High-Z

Notes: 1. Refer to the recommended DC operating condition.2. × : Don’t care3. This function is supported by only the HN58C257A series.

Absolute Maximum Ratings

Parameter Symbol Value Unit

Power supply voltage relative to VSS VCC –0.6 to +7.0 V

Input voltage relative to VSS Vin –0.5*1 to +7.0*3 V

Operating temperature range*2 Topr 0 to +70 °C

Storage temperature range Tstg –55 to +125 °C

Notes: 1. Vin min = –3.0 V for pulse width ≤ 50 ns2. Including electrical characteristics and data retention3. Should not exceed VCC + 1 V.


5

Recommended DC Operating Conditions

Parameter Symbol Min Typ Max Unit

Supply voltage VCC 4.5 5.0 5.5 V

VSS 0 0 0 V

Input voltage VIL –0.3*1 — 0.8 V

VIH 2.2 — VCC + 0.3*2 V

VH*3 VCC – 0.5 — VCC + 1.0 V

Operating temperature Topr 0 — 70 °C

Notes: 1. VIL min: –1.0 V for pulse width ≤ 50 ns.2. VIH max: VCC + 1.0 V for pulse width ≤ 50 ns.3. This function is supported by only the HN58C257A series.

DC Characteristics (Ta = 0 to +70°C, VCC = 5.0 V±10%)

Parameter Symbol Min Typ Max Unit Test conditions

Input leakage current ILI — — 2*1 µA VCC = 5.5 V, Vin = 5.5 V

Output leakage current ILO — — 2 µA VCC = 5.5 V, Vout = 5.5/0.4 V

Standby VCC current ICC1 — — 20 µA CE = VCC

ICC2 — — 1 mA CE = VIH

Operating VCC current ICC3 — — 12 mA Iout = 0 mA, Duty = 100%,Cycle = 1 µs at VCC = 5.5 V

— — 30 mA Iout = 0 mA, Duty = 100%,Cycle = 85 ns at VCC = 5.5 V

Output low voltage VOL — — 0.4 V IOL = 2.1 mA

Output high voltage VOH 2.4 — — V IOH = –400 µA

Note: 1. ILI on RES = 100 µA max (only the HN58C257A series)

Capacitance (Ta = +25°C, f = 1 MHz)

Parameter Symbol Min Typ Max Unit Test conditions

Input capacitance*1 Cin — — 6 pF Vin = 0 V

Output capacitance*1 Cout — — 12 pF Vout = 0 V

Note: 1. This parameter is periodically sampled and not 100% tested.


6

AC Characteristics (Ta = 0 to +70°C, VCC = 5 V±10%)

Test Conditions

• Input pulse levels: 0.4 V to 3.0 V0 V to VCC (RES pin*2)

• Input rise and fall time: ≤ 5 ns

• Input timing reference levels: 0.8, 2.0 V

• Output load: 1TTL Gate +100 pF

• Output reference levels: 1.5 V, 1.5 V

Read Cycle

HN58C256A/HN58C257A

-85 -10

Parameter Symbol Min Max Min Max Unit Test conditions

Address to output delay tACC — 85 — 100 ns CE = OE = VIL,WE = VIH

CE to output delay tCE — 85 — 100 ns OE = VIL, WE = VIH

OE to output delay tOE 10 40 10 50 ns CE = VIL, WE = VIH

Address to output hold tOH 0 — 0 — ns CE = OE = VIL,WE = VIH

OE (CE) high to output float*1 tDF 0 40 0 40 ns CE = VIL, WE = VIH

RES low to output float*1, 2 tDFR 0 350 0 350 ns CE = OE = VIL,WE = VIH

RES to output delay*2 tRR 0 450 0 450 ns CE = OE = VIL,WE = VIH


7

Write Cycle

Parameter Symbol Min* 3 Typ Max Unit Test conditions

Address setup time tAS 0 — — ns

Address hold time tAH 50 — — ns

CE to write setup time (WE controlled) tCS 0 — — ns

CE hold time (WE controlled) tCH 0 — — ns

WE to write setup time (CE controlled) tWS 0 — — ns

WE hold time (CE controlled) tWH 0 — — ns

OE to write setup time tOES 0 — — ns

OE hold time tOEH 0 — — ns

Data setup time tDS 50 — — ns

Data hold time tDH 0 — — ns

WE pulse width (WE controlled) tWP 100 — — ns

CE pulse width (CE controlled) tCW 100 — — ns

Data latch time tDL 50 — — ns

Byte load cycle tBLC 0.2 — 30 µs

Byte load window tBL 100 — — µs

Write cycle time tWC — — 10*4 ms

Time to device busy tDB 120 — — ns

Write start time tDW 0*5 — — ns

Reset protect time*2 tRP 100 — — µs

Reset high time*2, 6 tRES 1 — — µs

Notes: 1. tDF and tDFR are defined as the time at which the outputs achieve the open circuit conditions andare no longer driven.

2. This function is supported by only the HN58C257A series.3. Use this device in longer cycle than this value.4. tWC must be longer than this value unless polling techniques or RDY/Busy (only the HN58C257A

series) are used. This device automatically completes the internal write operation within thisvalue.

5. Next read or write operation can be initiated after tDW if polling techniques or RDY/Busy (only theHN58C257A series) are used.

6. This parameter is sampled and not 100% tested.7. A6 through A14 are page address and these addresses are latched at the first falling edge of

WE.8. A6 through A14 are page address and these addresses are latched at the first falling edge of

CE.9. See AC read characteristics.


8

Read Timing Waveform

Address

CE

OE

WE

Data Out

High

Data out valid

tACC

tCE

tOE

tOH

tDF

tRR

tDFR

RES *2


9

Byte Write Timing Waveform (1) (WE Controlled)

Address

CE

WE

OE

Din

RDY/Busy *2

tWC

tCHtAHtCS

tAStWP

tOEH

tBL

tOES

tDS tDH

tDB

tRP

RES *2

VCC

tRES

High-Z High-Z

tDW


10

Byte Write Timing Waveform (2) (CE Controlled)

Address

CE

WE

OE

Din

RDY/Busy *2

tWCtAHtWS

tAS

tOEH

tWH

tOES

tDS tDH

tDB

tRP

RES *2

VCC

tCW

tBL

tDW

tRES

High-Z High-Z


11

Page Write Timing Waveform (1) (WE Controlled)

Address A0 to A14

WE

CE

OE

Din

RDY/Busy *2

tAStAH tBL

tWC

tOEH

tDH

tDB

tOES

tRP

tRESRES *2

VCC

tCHtCS

tWP

tDL tBLC

tDS

tDW

High-Z High-Z

*7


12

Page Write Timing Waveform (2) (CE Controlled)

Address A0 to A14

WE

CE

OE

Din

RDY/Busy *2

tAStAH tBL

tWC

tOEH

tDH

tDB

tOES

tRP

tRESRES *2

VCC

tWHtWS

tCW

tDL tBLC

tDS

tDW

High-Z High-Z

*8


13

Data Polling Timing Waveform

tCEtOEH

tWC

tDW

tOES

Address

CE

WE

OE

I/O7

tOE

Din X

An An

Dout X Dout X

*9

*9

An


14

Toggle bit

This device provide another function to determine the internal programming cycle. If the EEPROM is setto read mode during the internal programming cycle, I/O6 will charge from “1” to “0” (toggling) for eachread. When the internal programming cycle is finished, toggling of I/O6 will stop and the device can beaccessible for next read or program.

Toggle bit Waveform

Notes: 1. I/O6 beginning state is "1".

2. I/O6 ending state will vary.

3. See AC read characteristics.

4. Any address location can be used, but the address must be fixed.

WE

tOES

OE

CE

DoutI/O6 Dout Dout Dout

Next mode

tOE

tCE

tDWtWC

tOEH

*1 *2 *2

Address

*3

*3

*4

Din


15

Software Data Protection Timing Waveform (1) (in protection mode)

V

CE

WE

Address Data

5555 AA

2AAA 55

5555 A0

tBLC tWC

CC

Write address Write data

Software Data Protection Timing Waveform (2) (in non-protection mode)

V

CE

WE

Address Data

tWCCC

Normal active mode

5555 AA

2AAA 55

5555 80

5555 AA

2AAA 55

5555 20


16

Functional Description

Automatic Page Write

Page-mode write feature allows 1 to 64 bytes of data to be written into the EEPROM in a single writecycle. Following the initial byte cycle, an additional 1 to 63 bytes can be written in the same manner. Eachadditional byte load cycle must be started within 30 µs from the preceding falling edge of WE or C E.When CE or WE is high for 100 µs after data input, the EEPROM enters write mode automatically and theinput data are written into the EEPROM.

Data Polling

Data polling indicates the status that the EEPROM is in a write cycle or not. If EEPROM is set to readmode during a write cycle, an inversion of the last byte of data outputs from I/O7 to indicate that theEEPROM is performing a write operation.

RDY/Busy Signal (only the HN58C257A series)

RDY/Busy signal also allows status of the EEPROM to be determined. The RDY/Busy signal has highimpedance except in write cycle and is lowered to VOL after the first write signal. At the end of a writecycle, the RDY/Busy signal changes state to high impedance.

RES Signal (only the HN58C257A series)

When RES is low, the EEPROM cannot be read or programmed. Therefore, data can be protected bykeeping RES low when VCC is switched. RES should be high during read and programming because itdoesn't provide a latch function.

V

Program inhibit

CC

RES

Program inhibit

Read inhibit Read inhibit


17

WE, CE Pin Operation

During a write cycle, addresses are latched by the falling edge of WE or CE, and data is latched by therising edge of WE or CE.

Write/Erase Endurance and Data Retention Time

The endurance is 105 cycles in case of the page programming and 104 cycles in case of the byteprogramming (1% cumulative failure rate). The data retention time is more than 10 years when a device ispage-programmed less than 104 cycles.

Data Protection

1. Data Protection against Noise on Control Pins (CE, OE, WE) during Operation

During readout or standby, noise on the control pins may act as a trigger and turn the EEPROM toprogramming mode by mistake.

To prevent this phenomenon, this device has a noise cancellation function that cuts noise if its width is 20ns or less.

Be careful not to allow noise of a width of more than 20 ns on the control pins.

WECE

OEV

0 V

V0 V

20 ns max

IH

IH


18

2. Data Protection at VCC On/Off

When VCC is turned on or off, noise on the control pins generated by external circuits (CPU, etc) may act asa trigger and turn the EEPROM to program mode by mistake. To prevent this unintentional programming,the EEPROM must be kept in an unprogrammable state while the CPU is in an unstable state.

Note: The EEPROM should be kept in unprogrammable state during VCC on/off by using CPU RESETsignal.

VCC

CPU RESET

Unprogrammable Unprogrammable* *

(1) Protection by CE, OE, WE

To realize the unprogrammable state, the input level of control pins must be held as shown in the tablebelow.

CE VCC × ×

OE × VSS ×

WE × × VCC

×: Don’t care.VCC: Pull-up to VCC level.VSS: Pull-down to VSS level.


19

(2) Protection by RES (only the HN58C257A series)

The unprogrammable state can be realized by that the CPU’s reset signal inputs directly to the EEPROM’sRES pin. RES should be kept VSS level during VCC on/off.

The EEPROM breaks off programming operation when RES becomes low, programming operation doesn’tfinish correctly in case that RES falls low during programming operation. RES should be kept high for 10ms after the last data input.

VCC

RES

WE or CE

100 µs min 10 ms min1 µs min

Program inhibit Program inhibit


20

3. Software data protection

To prevent unintentional programming, this device has the software data protection (SDP) mode. The SDPis enabled by inputting the following 3 bytes code and write data. SDP is not enabled if only the 3 bytescode is input. To program data in the SDP enable mode, 3 bytes code must be input before write data.

Data

AA↓ 55↓

A0↓

Write data

Address

5555↓

2AAA ↓

5555↓

Write address Normal data input

The SDP mode is disabled by inputting the following 6 bytes code. Note that, if data is input in the SDPdisable cycle, data can not be written.

Data

AA ↓ 55 ↓ 80 ↓

AA ↓ 55 ↓ 20

Address

5555↓

2AAA↓

5555↓

5555↓

2AAA↓

5555

The software data protection is not enabled at the shipment.

Note: There are some differences between Hitachi’s and other company’s for enable/disable sequence ofsoftware data protection. If there are any questions , please contact with Hitachi sales offices.


21

Package Dimensions

HN58C256AP Series (DP-28)

0.51

Min

2.54

Min

0.25+ 0.11– 0.05

2.54 ± 0.25 0.48 ± 0.100° – 15°

15.241.2

35.6

36.5 Max

13.4

14

.6 M

ax

1 14

1528

5.70

Max1.9 Max

Hitachi CodeJEDECEIAJWeight (reference value)

DP-28—Conforms4.6 g

Unit: mm


22

Package Dimensions (cont.)

HN58C256AFP Series (FP-28D)

0° – 8°0.

17 ±

0.0

5

1.0 ± 0.2

0.20

± 0

.10

2.50

Max

8.4

18.3

18.8 Max

1.12 Max

28 15

1 14 11.8 ± 0.3

1.7

0.20

0.15

M

1.27

0.40 ± 0.080.38 ± 0.06

0.15

± 0

.04

Hitachi Code JEDEC EIAJ Weight (reference value)

FP-28D Conforms — 0.7 g

Unit: mm

Dimension including the plating thicknessBase material dimension


23


HN58C256AT Series (TFP-28DB)

0.10 M

0.55

8.00

0.22 ± 0.08

13.40 ± 0.30

0.17

± 0

.05

0.13

1.20

Max

11.8

0

0° – 5°

28

1 14

158.20 Max

0.10 +0.

07

–0.0

8 0.50 ± 0.10

0.800.45 Max


TFP-28DB — — 0.23 g

0.20 ± 0.06

0.15

± 0

.04

Unit: mm



24


HN58C257AT Series (TFP-32DA)


TFP-32DA Conforms Conforms 0.26 g

0.10

0.08 M

0.50

8.00

0.22 ± 0.08

14.00 ± 0.20

1.20

Max

12.4

0 32

1 16

17

0.17

± 0

.05

0.13

± 0

.05 0° – 5°

8.20 Max

0.45 Max

0.50 ± 0.10

0.800.20 ± 0.06

0.12

5 ±

0.04

Unit: mm



25

When using this document, keep the following in mind:

1. This document may, wholly or partially, be subject to change without notice.

2. All rights are reserved: No one is permitted to reproduce or duplicate, in any form, the whole or part ofthis document without Hitachi’s permission.

3. Hitachi will not be held responsible for any damage to the user that may result from accidents or anyother reasons during operation of the user’s unit according to this document.

4. Circuitry and other examples described herein are meant merely to indicate the characteristics andperformance of Hitachi’s semiconductor products. Hitachi assumes no responsibility for any intellectualproperty claims or other problems that may result from applications based on the examples describedherein.

5. No license is granted by implication or otherwise under any patents or other rights of any third party orHitachi, Ltd.

6. MEDICAL APPLICATIONS: Hitachi’s products are not authorized for use in MEDICALAPPLICATIONS without the written consent of the appropriate officer of Hitachi’s sales company.Such use includes, but is not limited to, use in life support systems. Buyers of Hitachi’s products arerequested to notify the relevant Hitachi sales offices when planning to use the products in MEDICALAPPLICATIONS.

Hitachi, Ltd. Semiconductor & IC Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100, Japan Tel: Tokyo (03) 3270-2111 Fax: (03) 3270-5109

For further information write to: Hitachi America, Ltd. Semiconductor & IC Div. 2000 Sierra Point Parkway Brisbane, CA. 94005-1835 U S A Tel: 415-589-8300 Fax: 415-583-4207

Hitachi Europe GmbH Continental Europe Dornacher Straße 3 D-85622 Feldkirchen München Tel: 089-9 91 80-0 Fax: 089-9 29 30-00

Hitachi Europe Ltd. Electronic Components Div. Northern Europe Headquarters Whitebrook Park Lower Cookham Road Maidenhead Berkshire SL6 8YA United Kingdom Tel: 01628-585000 Fax: 01628-585160

Hitachi Asia Pte. Ltd. 16 Collyer Quay #20-00 Hitachi Tower Singapore 049318 Tel: 535-2100 Fax: 535-1533 Hitachi Asia (Hong Kong) Ltd. Unit 706, North Tower, World Finance Centre, Harbour City, Canton Road Tsim Sha Tsui, Kowloon Hong Kong Tel: 27359218 Fax: 27306071

Copyright © Hitachi, Ltd., 1997. All rights reserved. Printed in Japan.


26

Revision Record

Rev. Date Contents of Modification Drawn by Approved by

0.0 Jun. 19, 1995 Initial issue Y. Nagai T. Muto

1.0 May. 17, 1996 Change of formatAbsolute Maximun Ratings

Addition of note 4Recommended DC Operating Conditions

VIH (min): 3.0 V to 2.2 VAC Characteristics

VOH (min): VCC × 0.8 V to 2.4 VAC Characteristics

Input pulse levels: 0 V to 3.0 V to 0.4 V to 3.0 VData Polling Timing Waveform

Addition of note 1Toggle bit Waveform

Addition of note 4

Y. Nagai T. Wada

2.0 Feb. 27, 1997 Recommended DC Operating ConditionsVIL (max): 0.6 V to 0.8 V

Functional DescriptionData Protection 3: Addition of note

Y. Nagai K. Furusawa

3.0 May. 20, 1997 Functional DescriptionData Protection 3: Change of Description

M. Terasawa K. Furusawa

4.0 Oct. 24, 1997 Timing WaveformsRead Timing Waveform: Correct error

IRF540IRF540FI

N - CHANNEL ENHANCEMENT MODEPOWER MOS TRANSISTORS

TYPICAL RDS(on) = 0.045 Ω AVALANCHE RUGGED TECHNOLOGY 100% AVALANCHE TESTED REPETITIVE AVALANCHE DATA AT 100oC LOW GATE CHARGE HIGH CURRENT CAPABILITY 175oC OPERATING TEMPERATURE

APPLICATIONS HIGH CURRENT, HIGH SPEED SWITCHING SOLENOID AND RELAY DRIVERS REGULATORS DC-DC & DC-AC CONVERTERS MOTOR CONTROL, AUDIO AMPLIFIERS AUTOMOTIVE ENVIRONMENT (INJECTION,

ABS, AIR-BAG, LAMPDRIVERS, Etc.)

INTERNAL SCHEMATIC DIAGRAM

12

3

TO-220 ISOWATT220

July 1993

TYPE VDSS RDS(on) ID

IRF540IRF540FI

100 V100 V

< 0.077 Ω< 0.077 Ω

30 A16 A

ABSOLUTE MAXIMUM RATINGS

Symbol Parameter Value Unit

IRF540 IRF540FI

VDS Drain-source Voltage (VGS = 0) 100 V

VDG R Drain- gate Voltage (RGS = 20 kΩ) 100 V

VGS Gate-source Voltage ± 20 V

ID Drain Current (cont.) at Tc = 25 oC 30 16 A

ID Drain Current (cont.) at Tc = 100 oC 21 11 A

IDM(•) Drain Current (pulsed) 120 120 A

Ptot Total Dissipation at Tc = 25 oC 150 45 W

Derating Factor 1 0.3 W/oC

VISO Insulat ion Withstand Voltage (DC) ⎯ 2000 V

Tstg Storage Temperature -65 to 175 oC

Tj Max. Operat ing Junction Temperature 175 oC(•) Pulse width limited by safe operating area

12

3

1/9

THERMAL DATA

TO-220 ISOWATT220

Rthj-case Thermal Resistance Junct ion-case Max 1 3.33 oC/W

Rthj-amb

Rthc-s

Tl

Thermal Resistance Junct ion-ambient MaxThermal Resistance Case-sink TypMaximum Lead Temperature For Soldering Purpose

62.50.5300

oC/WoC/W

oC

AVALANCHE CHARACTERISTICS

Symbol Parameter Max Value Unit

IAR Avalanche Current, Repetitive or Not-Repetitive(pulse width limited by Tj max, δ < 1%)

30 A

EAS Single Pulse Avalanche Energy(starting Tj = 25 oC, ID = IAR, VDD = 25 V)

200 mJ

EAR Repetitive Avalanche Energy(pulse width limited by Tj max, δ < 1%)

50 mJ

IAR Avalanche Current, Repetitive or Not-Repetitive(Tc = 100 oC, pulse width limited by Tj max, δ < 1%)

21 A

ELECTRICAL CHARACTERISTICS (Tcase = 25 oC unless otherwise specified)OFF

Symbol Parameter Test Conditions Min. Typ. Max. Unit

V(BR)DSS Drain-sourceBreakdown Voltage

ID = 250 μA VGS = 0 100 V

IDSS Zero Gate VoltageDrain Current (VGS = 0)

VDS = Max RatingVDS = Max Rating x 0.8 Tc = 125 oC

2501000

μAμA

IGSS Gate-body LeakageCurrent (VDS = 0)

VGS = ± 20 V ± 100 nA

ON (∗)


VGS(th) Gate Threshold Voltage VDS = VGS ID = 250 μA 2 2.9 4 V

RDS(on) Static Drain-source OnResistance

VGS = 10V ID = 17 A 0.045 0.077 Ω

ID(on) On State Drain Current VDS > ID(on) x RDS(on)max VGS = 10 V 30 A

DYNAMIC


gfs (∗) ForwardTransconductance

VDS > ID(on) x RDS(on)max ID = 17 A 10 18 S

Ciss

Coss

Crss

Input CapacitanceOutput CapacitanceReverse TransferCapacitance

VDS = 25 V f = 1 MHz VGS = 0 1600460140

2100600200

pFpFpF

IRF540/FI

2/9

ELECTRICAL CHARACTERISTICS (continued)SWITCHING RESISTIVE LOAD


td(on)

trtd(off )

tf

Turn-on TimeRise TimeTurn-off Delay TimeFall Time

VDD = 50 V ID = 5 ARi = 50 Ω VGS = 10 V(see test circuit)

55110290125

80160410180

nsnsnsns

Qg

Qgs

Qgd

Total Gate ChargeGate-Source ChargeGate-Drain Charge

ID = 30 A VGS = 10 VVDD = Max Rating x 0.8(see test circuit)

551126

80 nCnCnC

SOURCE DRAIN DIODE


ISD

ISDM(•)Source-drain CurrentSource-drain Current(pulsed)

30120

AA

VSD (∗) Forward On Voltage ISD = 30 A VGS = 0 1.6 V

trr

Qrr

Reverse RecoveryTimeReverse RecoveryCharge

ISD = 30 A di/dt = 100 A/μsTj = 150 oC VDD = 50 V

140

0.7

ns

μC

(∗) Pulsed: Pulse duration = 300 μs, duty cycle 1.5 %(•) Pulse width limited by safe operating area

Safe Operating Area for TO-220 Package Safe Operating Area for ISOWATT220 Package

IRF540/FI

3/9

Thermal Impedance for TO-220 Package

Derating Curve for TO-220 Package

Output Characteristics

Thermal Impedance for ISOWATT220 Package

Derating Curve for ISOWATT220 Package

Transfer Characteristics

IRF540/FI

4/9

Transconductance Static Drain-source On Resistance

Gate Charge vs Gate-source Voltage Capacitance Variations

Normalized On Resistance vs TemperatureNormalized Gate Threshold Voltage vsTemperature

IRF540/FI

5/9

Source-drain Diode Forward Characteristics

Unclamped Inductive Load Test Circuit Unclamped Inductive Waveforms

Switching Time Test Circuit Gate Charge Test Circuit

IRF540/FI

6/9

DIM.mm inch

MIN. TYP. MAX. MIN. TYP. MAX.

A 4.40 4.60 0.173 0.181

C 1.23 1.32 0.048 0.051

D 2.40 2.72 0.094 0.107

D1 1.27 0.050

E 0.49 0.70 0.019 0.027

F 0.61 0.88 0.024 0.034

F1 1.14 1.70 0.044 0.067

F2 1.14 1.70 0.044 0.067

G 4.95 5.15 0.194 0.203

G1 2.4 2.7 0.094 0.106

H2 10.0 10.40 0.393 0.409

L2 16.4 0.645

L4 13.0 14.0 0.511 0.551

L5 2.65 2.95 0.104 0.116

L6 15.25 15.75 0.600 0.620

L7 6.2 6.6 0.244 0.260

L9 3.5 3.93 0.137 0.154

DIA. 3.75 3.85 0.147 0.151

L6

A

C D

E

D1

F

G

L7

L2

Dia.

F1

L5

L4

H2

L9

F2

G1

TO-220 MECHANICAL DATA

P011C

IRF540/FI

7/9

DIM.mm inch

MIN. TYP. MAX. MIN. TYP. MAX.

A 4.4 4.6 0.173 0.181

B 2.5 2.7 0.098 0.106

D 2.5 2.75 0.098 0.108

E 0.4 0.7 0.015 0.027

F 0.75 1 0.030 0.039

F1 1.15 1.7 0.045 0.067

F2 1.15 1.7 0.045 0.067

G 4.95 5.2 0.195 0.204

G1 2.4 2.7 0.094 0.106

H 10 10.4 0.393 0.409

L2 16 0.630

L3 28.6 30.6 1.126 1.204

L4 9.8 10.6 0.385 0.417

L6 15.9 16.4 0.626 0.645

L7 9 9.3 0.354 0.366

Ø 3 3.2 0.118 0.126

L2

A

B

D

E

H G

L6

Ø F

L3

G1

1 2 3

F2

F1

L7

L4

ISOWATT220 MECHANICAL DATA

P011G

IRF540/FI

8/9

Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsability for theconsequences of use of such information nor for any infringement of patents or other rights of third parties which may results from its use. Nolicense is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics.Specificationsmentionedin this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied.SGS-THOMSON Microelectronicsproducts are not authorized for use as critical components in life supportdevices or systems without expresswritten approval of SGS-THOMSON Microelectonics.

© 1994 SGS-THOMSON Microelectronics - All Rights Reserved

SGS-THOMSON Microelectronics GROUP OF COMPANIESAustralia - Brazil - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands -

Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A

IRF540/FI

9/9

Semiconductor Group 1

SFH 309SFH 309 FA

NPN-Silizium-FototransistorSilicon NPN Phototransistor

Wesentliche Merkmale

Speziell geeignet für Anwendungen imBereich von 380 nm bis 1180 nm(SFH 309) und bei 880 nm (SFH 309 FA)

Hohe Linearität 3 mm-Plastikbauform im LED-Gehäuse Gruppiert lieferbar

Anwendungen

Lichtschranken für Gleich- undWechsellichtbetrieb

Industrieelektronik “Messen/Steuern/Regeln”

Features

Especially suitable for applications from380 nm to 1180 nm (SFH 309) and of880 nm (SFH 309 FA)

High linearity 3 mm LED plastic package Available in groups

Applications

Photointerrupters Industrial electronics For control and drive circuits

SFH 309SFH 309 FA

Maße in mm, wenn nicht anders angegeben/Dimensions in mm, unless otherwise specifiedfe

of66

53fe

o066

53

01.97


SFH 309SFH 309 FA

1) Eine Lieferung in dieser Gruppe kann wegen Ausbeuteschwankungen nicht immer sichergestellt werden.Wir behalten uns in diesem Fall die Lieferung einer Ersatzgruppe vor.

1) Supplies out of this group cannot always be guaranteed due to unforseeable spread of yield. In this case wewill reserve us the right of delivering a substitute group.

TypType

BestellnummerOrdering Code

Typ (*vorher)Type (*formerly)

BestellnummerOrdering Codes

SFH 309 Q62702-P859 SFH 309 FA(*SFH 309 F)

Q62702-P941

SFH 309-3 Q62702-P997 SFH 309 FA-2(*SFH 309 F-2)

Q62702-P174

SFH 309-4 Q62702-P998 SFH 309 FA-3(*SFH 309 F-3)

Q62702-P176

SFH 309-5 Q62702-P999 SFH 309 FA-4(*SFH 309 F-4)

Q62702-P178

SFH 309-61) Q62702-P1000 SFH 309 FA-5(*SFH 309 F-51))

Q62702-P180

GrenzwerteMaximum Ratings

BezeichnungDescription

SymbolSymbol

WertValue

EinheitUnit

Betriebs- und LagertemperaturOperating and storage temperature range

Top; Tstg – 55 ... + 100 °C

Löttemperatur bei TauchlötungLötstelle ≥ 2 mm vom Gehäuse,Lötzeit t ≤ 5 sDip soldering temperature ≥ 2 mm distancefrom case bottom, soldering time t ≤ 5 s

TS 260 °C

Löttemperatur bei KolbenlötungLötstelle ≥ 2 mm vom Gehäuse,Lötzeit t ≤ 3 sIron soldering temperature ≥ 2 mm distancefrom case bottom, soldering time t ≤ 3 s

TS 300 °C

Kollektor-EmitterspannungCollector-emitter voltage

VCE 35 V

KollektorstromCollector current

IC 15 mA

Kollektorspitzenstrom, τ < 10 µsCollector surge current

ICS 75 mA


SFH 309SFH 309 FA

Verlustleistung, TA = 25 °CTotal power dissipation

Ptot 165 mW

WärmewiderstandThermal resistance

RthJA 450 K/W

Kennwerte (TA = 25 °C, λ = 950 nm)Characteristics


SymbolSymbol

WertValue

EinheitUnit

SFH 309 SFH 309 FA

Wellenlänge der max. FotoempfindlichkeitWavelength of max. sensitivity

λS max 860 900 nm

Spektraler Bereich der FotoempfindlichkeitS = 10 % von Smax

Spectral range of sensitivityS = 10 % of Smax

λ 380 ... 1150 730 ... 1120 nm

Bestrahlungsempfindliche Fläche (∅ 240 µm)Radiant sensitive area

A 0.2 0.2 mm2

Abmessung der ChipflächeDimensions of chip area

L × BL × W

0.45 × 0.45 0.45 × 0.45 mm × mm

Abstand Chipoberfläche zu Gehäuseober-flächeDistance chip front to case surface

H 2.4 ... 2.8 2.4 ... 2.8 mm

HalbwinkelHalf angle

ϕ ± 12 ± 12 Graddeg.

Kapazität, VCE = 0 V, f = 1 MHz, E = 0Capacitance

CCE 5.0 5.0 pF

DunkelstromDark currentVCE = 25 V, E = 0

ICEO 1 (≤ 200) 1 (≤ 200) nA

GrenzwerteMaximum Ratings (cont’d)


SymbolSymbol

WertValue

EinheitUnit


SFH 309SFH 309 FA

Die Fototransistoren werden nach ihrer Fotoempfindlichkeit gruppiert und mit arabischenZiffern gekennzeichnet.The phototransistors are grouped according to their spectral sensitivity and distinguishedby arabian figures.

1) IPCEmin ist der minimale Fotostrom der jeweiligen Gruppe1) IPCEmin is the min. photocurrent of the specified group

Directional characteristics Srel = f (ϕ)


SymbolSymbol

WertValue

EinheitUnit

-2 -3 -4 -5

Fotostrom, λ = 950 nmPhotocurrentEe = 0.5 mW/cm2, VCE = 5 VSFH 309:Ev = 1000 Ix, Normlicht/standard light A, VCE = 5 V

IPCE

IPCE

0.4 ... 0.8

1.5

0.63 ... 1.25

2.8

1.0 ... 2.0

4.5

1.6 ... 3.2

7.2

mA

mA

Anstiegszeit/AbfallzeitRise and fall timeIC = 1 mA, VCC = 5 V,RL = 1 kΩ

tr, tf 5 6 7 8 µs

Kollektor-Emitter-SättigungsspannungCollector-emitter saturationvoltageIC = IPCEmin

1) × 0.3,Ee = 0.5 mW/cm2

VCEsat 200 200 200 200 mV


SFH 309SFH 309 FA


SFH 309SFH 309 FA

Relative spectral sensitivity ,SFH 309 Srel = f (λ)

Total power dissipationPtot = f (TA)

Dark currentICEO = f (TA), VCE = 25 V, E = 0

Relative spectral sensitivity ,SFH 309 FA Srel = f (λ)

PhotocurrentIPCE = f (VCE), Ee = Parameter

CapacitanceCCE= f (VCE), f = 1 MHz, E = 0

PhotocurrentIPCE = f (Ee), VCE = 5 V

Dark currentICEO = f (VCE), E = 0

PhotocurrentIPCE/IPCE25

o = f (TA), VCE = 5 V

P-CHANNEL ENHANCEMENT

MODE VERTICAL DMOS FETISSUE 2 – MARCH 94

FEATURES* 60 Volt VDS* RDS(on)=5Ω

ABSOLUTE MAXIMUM RATINGS.

PARAMETER SYMBOL VALUE UNIT

Drain-Source Voltage VDS -60 V

Continuous Drain Current at Tamb=25°C ID -280 mA

Pulsed Drain Current IDM -4 A

Gate Source Voltage VGS ± 20 V

Power Dissipation at Tamb=25°C Ptot 700 mW

Operating and Storage Temperature Range Tj:Tstg -55 to +150 °C

ELECTRICAL CHARACTERISTICS (at Tamb = 25°C unless otherwise stated).

PARAMETER SYMBOL MIN. MAX. UNIT CONDITIONS.

Drain-Source BreakdownVoltage

BVDSS -60 V ID=-1mA, VGS=0V

Gate-Source ThresholdVoltage

VGS(th) -1.5 -3.5 V ID=-1mA, VDS= VGS

Gate-Body Leakage IGSS 20 nA VGS=± 20V, VDS=0V

Zero Gate Voltage DrainCurrent

IDSS -0.5-100

µAµA

VDS=-60 V, VGS=0VDS=-48 V, VGS=0V, T=125°C(2)

On-State Drain Current(1) ID(on) -1 A VDS=-18 V, VGS=-10V

Static Drain-Source On-StateResistance (1)

RDS(on) 5 Ω VGS=-10V,ID=-500mA

Forward Transconductance(1)(2)

gfs 150 mS VDS=-18V,ID=-500mA

Input Capacitance (2) Ciss 100 pF

Common Source OutputCapacitance (2)

Coss 60 pF VDS=-18V, VGS=0V, f=1MHz

Reverse TransferCapacitance (2)

Crss 20 pF

Turn-On Delay Time (2)(3) td(on) 7 ns

VDD ≈-18V, ID=-500mARise Time (2)(3) tr 15 ns

Turn-Off Delay Time (2)(3) td(off) 12 ns

Fall Time (2)(3) tf 15 ns

(1) Measured under pulsed conditions. Width=300µs. Duty cycle ≤2%(2) Sample test.

(3)

Switching times measured with 50Ω source impedance and <5ns rise time on a pulse generator

E-Line

TO92 Compatible

ZVP2106A

3-417

D G S

TYPICAL CHARACTERISTICS

Output Characteristics

VDS - Drain Source Voltage (Volts)

ID(O

n) -O

n-S

tate

Dra

in C

urre

nt (

Am

ps)

Transfer Characteristics

Normalised R DS(on) and VGS(th) vs Temperature

Nor

mal

ised

RD

S(o

n)an

d V

GS

(th

)

-40 -20 0 20 40 60 80 120100 140 160

2.4

2.2

2.0

1.8

1.6

1.4

1.2

1.0

0.6

0.8

Drain

-Sourc

e Resis

tance

RDS(o

n)

Gate Threshold Voltage VGS(th)

ID=-0.5A

0 -2 -4 -6 -8 -100 -10 -20 -30 -40 -50

Saturation Characteristics

VD

S- D

rain

Sou

rce

Vo

ltag

e (V

olt

s)

Voltage Saturation Characteristics

VGS-Gate Source Voltage (Volts)

-10V

ID(O

n)-O

n-S

tate

Dra

in C

urre

nt (

Am

ps)

VGS-Gate Source Voltage (Volts)

VGS=-10V

ID=-1mAVGS=VDS

-3.5

-3.0

-2.0

-0.5

0

-1.0

-2.5

-1.5

2.6

180

VGS=

-20V-14V

-5V

-6V

-7V

-4V-3.5V

-8V

VGS=-18V

ID(O

n) -O

n-S

tate

Dra

in C

urre

nt (

Am

ps)

VDS - Drain Source Voltage (Volts)

On-resistance v drain current

ID-Drain Current (Amps)

RD

S(O

N) -D

rain

So

urc

e R

esis

tan

ce (Ω

)

-0.1 -1.0

10

5

-2.0

-12V

-6V

-4V

0 -2 -4 -6 -8 -10

1

-10V-9V

-8V-7V

-5V

-9V

0

-0.6

-0.4

-0.2

-0.8

-1.6

-1.4-1.2

-1.0

-1.8

-2.0

0

-10

-6

-2

-4

-8

0 -2 -4 -6 -8 -10

ID=

-1A

-0.5A

-0.25A

-0.8

-0.6

-0.2

-0.4

VDS=-10V

-1.6

-1.4

-1.0

-1.2

-6V -7V VGS=-5V -8V -10V -9V

Tj-Junction Temperature (°C)

ZVP2106A

3-418

TYPICAL CHARACTERISTICS

Transconductance v drain current

ID- Drain Current (Amps)

gfs-

Tra

nsco

nduc

tanc

e (m

S)

0

Q-Charge (nC)

Transconductance v gate-source voltage

VGS-Gate Source Voltage (Volts)gf

s-Tr

ansc

ondu

ctan

ce (

mS

)

0 -10 -20 -30

VDS-Drain Source Voltage (Volts)

Capacitance v drain-source voltage

C-C

apac

itanc

e (p

F)

Coss

VG

S-G

ate

Sou

rce

Vol

tage

(V

olts

)

Gate charge v gate-source voltage

-6

-8

-10

-14

-16

-12

-4

-2

0

VDS= -20V -30V -50V

-40 -50 0.2 0.4 0.6 0.8 1.0 1.2

40

20

0

60Ciss

Crss

80

100

1.4 1.6 1.8 2.0 2.2 2.4

0 -0.2 -0.4 -0.6 -0.8 -1.0 -1.2 -1.4 -1.6 -1.8 -2.0

0

VDS=-10V200

150

100

50

250

300

0 -2 -4 -6 -8 -10

0

VDS=-10V

200

150

100

50

250

300

ZVP2106A

3-419