soc design 1

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SoC Design

CEG5010 Tutorial 7By K. H. Tsoi

Dept. Computer Science and EngineeringThe Chinese University of Hong Kong

2004-2005http://www.cse.cuhk.edu.hk/~ceg5010

Overview

Introduction to SoC in FPGAs The Suzaku board

Xilinx EDK Application: Hello World Application: User IP Adder


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Introduction to SoC

SoC = System on Chip

Inside a single chip Micro Processor Memory Buses I/O controller

Supporting tools Software/Hardware co-design

Micro Processor

Soft core: MicroBlaze Resident in reconfigurable logic

32-bit processor, 32 user registers Available in: VirtexE/II/II Pro/4, Spartan II/IIE/3

Hard core: PPC450 Dedicated VLSI core in FPGA chip IBM PPC450 core w/ MMU Available in: Virtex II Pro, Virtex 4


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Bus

Bridge between processor & other logics

PLB: Processor Local Bus (fast) (PPC only) Master/Slave interface Directly connected to processor 32-bit address, 64-bit data Data/Instruction memory for PPC

OPB: On-chip Peripheral Bus (slow) Connected to processor through PLB 32-bit address, 32-bit data

Bus (cont.)

DCR: Device Control Register Bus (PPC only) Between CPU's general purpose registers (GPRs) and the

DCR slave logic's device control registers (DCRs)

10-bit address, 32-bit data LMB: Local Memory Bus (fast) (MB only)

Connecting MicroBlaze instruction and data ports to BRAM FSL: Fast Simplex Link Bus (MB only)

Direct connection hardware core FIFO using SRL16 Point-to-Point, unidirectional communication

Single Master/Slave for each FSL


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Memory & I/O

On-chip memory:

BlockRAM, distribute RAM Off-chip memory:

SDRAM, DDRAM Compact Flash ROM

Rocket I/O

Suzaku Development Board


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Board Specification

Xilinx Spartan-3 (XC3S400-FT256-4C)

Crystal Oscillator: 3.6864MHz Power: DC 3.3V 350mA Free user I/O pin: 86 Configuration: JATG through TE7720 Reset: software reset

Pre-built: uCLinux running on MicroBlaze

Lab Environment


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Getting Start

Connect RS232C UART to PC serial port

Open Hyper Terminal on PC 115.2k bps, 8-bit data, 1-bit stop no parity, no flow control

Connect power (3.3V DC) to Suzaku Wait for Linux to boot Login

User: root Password: root

Programming the FPGA

Through FPGA/Linux (recommended) Upload CF image to personal web server

Configure the uCLinux eth0 interface Use the netflash utility in Linux to rewrite the

content of CF Through TE7720

Connect JTAG to CON2 and use LBPLAY2.EXE Directly to FPGA

Connect JTAG to CON7 and use IMPACT


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Suzaku MicorBlaze Memory MAP

Free0xFFFF FFFF0xFFFF A100

Boot Mode JumperLEDSoftware Reset

OPB-GPIO0xFFFF A0FF0xFFFF A000

Free0xFFFF 9FFF0xFFFF 3100

OPB-Interrupt Controller0xFFFF 30FF0xFFFF 3000


RS232COPB-UART Lite0xFFFF 20FF0xFFFF 2000


OPB-Timer0xFFFF 10FF0xFFFF 1000

Free0xFFFF 0FFF0xFFF0 0000

LAN ControllerOPB-EMC0xFFEF FFFF0xFFE0 0000

Free0xFFCF FFFF0xFF80 0000

FLASH Memory 4MByteOPB-EMC0xFF7F FFFF0xFF00 0000Free0xFEFF FFFF0x8100 0000

SDRAM 16MByteOPB-SDRAM Controller0x80FF FFFF0x8000 0000

Reserved0x7FFF FFFF0x0000 1000

BRAM0x0000 1FFF0x0000 0000

DevicePeripheralEnd AddressStart Address

Suzaku Flash Memory Map

User IPs should make use of the free slots inmemory map

New configuration (bitstream) should bedownloaded to 0x00000000 of Flash Memory

New uclinux kernel should be downloaded to0x000A0000 of Flash Memory

Do NOT confuse MB memory and Flash Memory

010000 (64KB)Config (for what?)0x003FFFFF0x003F0000

0x350000 (about 3.3M)uC Linux + User application image (create your own)0x003EFFFF0x000A0000

0x20000 (128KB)Bootloader (dont touch)0x0009FFFF0x00080000

0x80000 (512KB)FPGA bitstream0x0007FFFF0x00000000

SizeRegionEnd AddressStart Address


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Suzaku Booting Process

The configuration (i.e. address 0 of Flash

RAM) is loaded into FPGA via the TE7720 This configuration includes a simple

bootstrap (1st stage boot loader) in BRAM The 1st stage boot loader copies the 2nd stage

boot loader (in Flash RAM 0x0009FFFF) intoBRAM

The 2nd boot loader loads the Linux imageand starts the Linux boot sequence

EDK

Embedded Development Kit Xilinx software to build SoC applications

Uses Xilinx Platform Studio interface Abstraction platform descriptions

MHS: uP hardware specification Parameters and Port of each module

MSS: uP Software specification Specify which driver for which module

Wizard to import user peripherals/IPs


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EDK (cont.)

Board level simulation

Integrated C compiler Remote debug feature

Debug programs while running on target board

Standalone Applications

User application is only program run on uP Direct access to all system resources

Uses C library provided by Xilinx Compiled by Xilinxs modified GCC

E.g. mb_gcc Fast, simple, only Xilinx tool chain required Limited function: no server, no IPC, etc.

User must handle all communications


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Applications With OS

OS (e.g. uC Linux) loaded first into uP

User application run as a normal programunder the OS OS and user application all compiled using

cross development tools Complicated and may have OS overheads Feature rich: all you can get from an OS

User applications access hardware resourcethrough APIs included in the OS

Environment Setup: uC Linux

On a Linux PC Download cross development tool chain

microblaze-elf-tools-20040315.tar.gz

Download uCLinux distribution

uClinux-dist-20040408-suzaku4.tar.bz2 Download Hello demo program

hello.tar.gz Extract them all to user home directory Rename the uClinux directory

mv uClinux-dist-20040408-suzaku4 uClinux-dist Set the path environment

export PATH=$HOME/bin:$PATH


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Environment Setup: EDK/ProjNav

On a Windows PC

Download the FPGA Project

suzaku-20040611.zip

Extract to a working directory (no spaceallowed in path)

Make sure you have ISE 6.2i and EDK 6.2iinstalled

Use the 2005 version of Suzaku project if youhave ISE/EDK 6.3i

Environment Setup: Hardware

Make sure the Linux can boot up correctly Connect the Suzaku board to PC through

serial port Make sure the eth0 is up and connected to

network Make sure the power supply will not be

interrupted during process


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Application I: Hello World!

Only C program require

Left FPGA configuration untouched Step 1: make kernel image Step 2: make user application Step 3: create Linux image Step 4: download image to Flash memory

Step 5: reboot Step 6: test user application

cd uClinux-dist

make menuconfig1

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make clean; make dep; make

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Step 2: Compiling User Application

Change directory to Hello World demo cd $HOME/hello

Compile demo with ZFLAT compression make FLATFLAGS=-z Check the compression flag of executable

mb-flthdr hello

Install executable into destination make romfs

Check install complete ls ../uClinux-dist/romfs/bin/hello


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Step 3: Create Linux System Image

Change directory to uCLinux root

cd ../uClinux-dist Create the romfs.img and combine with the

linux.bin created in Step1 to from image.bin

make image

Check image file is updated

ls -l image

Upload the image.bin file to web server

Step 4: Download Image to Flash

Boot up the Suzaku board Login as root

Rewrite the Flash memory using netflash

netflash http://www.cse.cuhk.edu.hk/~khtsoi/image.bin

This takes 1 to 2 minutes to finish The system will reboot automatically and user

will see the login prompt again WARNNING: DO NOT interrupt power supply

when rewriting the Flash memory!!


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Step 6: Testing Application

Login as root

Run the demo application

hello

The following message will be displayed inconsole: Hello SUZAKU

Application II: User IP Adder

A hardware IP core is used in the demo 32-bit unsigned 2s complement adder

Using ISE 6.2i with EDK 6.2i

The EDK project is set to be a sub-module incomplete design

Xilinx Project navigator combines the followings: Netlist of MicroBlaze base system Netlist of user IP cores VHDL and UCF of top level Spartan3 design

User IP core connected to MicroBlaze through OPB

User application accesses IP core through themmap() API in uCLinux


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Procedures

Step 1: open demo project

Step 2: import IP template Step 3: create user IP Step 4: connect user IP to system Step 5: generate configuration file (bitstream) Step 6: create user application Step 7: create system image Step 8: download configuration to Flash Step 9: reboot and test

Step 1: Open Demo Project

Start EDK and open the XPS project

suzaku-20040611\xps_proj\xps_proj.xmp


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What is inside the FPGA?

Click the Applications tag, select the

Sources and open main.c This is the 1st stage boot loader which

resides inside the configurable data (BRAM)

and will be loaded to uP once boot This 1st stage boot loader is a stand alone

application The memory will be free and allocated later

by Linux

Step 2: Import IP Template

Select Tools Import Peripheral Wizard

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file:///C:/EDK/data/wizards/ip_moreinfo.htm


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PLB is not supportedby MicroBlaze


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These are I/O register ofour IP core

3 registers are requiredfor a full adder: A, B, S


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EDK will take care of these

We will synthesis the coreinside EDK environment


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Step 3: Create User IP

The newly created template is located in

MyProcessorIPLib\pcores\my_adder_v1_00_a There are two VHDL files in the directory

MyProcessorIPLib\pcores\my_adder_v1_00_a\hdl\vhdl\ my_adder.vhd : the wrapper connected to IPIF

user_logic.vhd : the wrapper for user logic All user IP designs should be included under user_logic.vhd

and left the my_adder.vhd untouched User can find many useful information in the user_logic.vhd

Already existed I/O registers and read/write control The memory map of the each register

All output signals are already driven as not to confuse uP


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The template allows uP write to and read

from all three registers We need to disable the write to sum register,

S, which should be generated by A+B The output of S must be registered as in the

original codes


In file user_logic.vhd Comment from line 176 and line 192196

Insert the following after line 201ADDER_CIRCUIT: process ( Bus2IP_Clk ) is

begin

if Bus2IP_Clk'event and Bus2IP_Clk = '1' then

if Bus2IP_Reset = '1' then

slv_reg2 '0');

else

slv_reg2


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Step 4: Connect User IP

We need to tell the system where and how

our IP will be connect to the other parts of thesystem

We use the first free slot in the system

memory 0x81000000 (as shown in previousslices)

Select Project Add/Edit Cores


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If any message about old core appear, just ignore it.


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Use Project

View BlockDiagram to verify theconnection.


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Step 5: Generate Configuration File

Execute under the Tools main menu

1. Generate Libraries and BSPs 2. Build All User Applications 3. Generate Netlist

You should not see any errors in the process All this can be done through the GUI

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Create a new Xilinx project to include the toplevel design and generated netlists

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Empty simulatorfield if you donthave ModelSim


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All VHDL filesare ready. Wedont need to

create new.


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Open top.vhd andtop.ucf from the

parent directory.

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Add the EDK project to the ISE project

Select top-imp (top.vhd) in Module View Select menu Project

Add Source Open the xps_proj.xmp in directory ..\xps_proj

Create Configuration bit file Select top-imp (top.vhd) in Module View Select Generate Programming File in Process View Select menu Process

Rerun All

The process should finish without error.


The top.bit file includes information header whichshould not appear in Flash

Download and compile the bit2flash utility

http://www.cse.cuhk.edu.hk/~ceg5010/bit2flash.c

gcc Wall o bit2flash bit2flash.c Use the nohead utility to remove the header

bit2flash top.bit new.bit Post the new configuration file new.bit on

personal web server WARNING: This is a alpha test program, use it at

your own risk.


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Step 6: Create User Application

We can start from the Hello world!

example by copying the hello directory tomy_adder directory

cp -r hello my_adder

Create a new C source file calledmy_adder.c

We will use the GPIO API in uCLinux toaccess our IP core


#include

#include

#include

#include

#include

int main(void) {

int fd;

int *p;fd = open("/dev/mem", O_RDWR);

p = (int *)mmap(0, 256, PROT_READ|PROT_WRITE,

MAP_PRIVATE, fd, 0x81000000);

if (p == MAP_FAILED) {

printf("Err: cannot access adder!\n");

return -1;

}

printf("input two numbers: ");

scanf("%d", p);

scanf("%d", p+1);

printf("%d + %d = %d\n", *p, *(p+1), *(p+2));

munmap(p, 256);close(fd);

return 0;

}


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Edit the Makefile

Replace all instances of hello withmy_adder

Compile the application

make -FLTFLAGS=-z

Install application and create system image

as in the Hello world! example

Step 7: Download Configuration

Login Suzaku as root Through network

netflash bn -r /dev/flash/fpgahttp://www.cse.cuhk.edu.hk/~khtsoi/new.bit

In local file system Store the new.bit in /var/tmp either through

system image or serial console

flashw -f /var/tmp/new.bit /dev/flash/fpga

WARNING: Do NOT reboot if download fails.

Try to download again.


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Step 8: Reboot and Test

Remember to download the system image

and reboot again as shown in previous slides After both FPGA configuration and system

image have been downloaded Login as root Run the your demo program

my_adder

Misc

A better way to install user applications: FTP. Bring up eth0 of Suzaku

Start FTP server in Suzaku: ftpd Upload user application to /var/tmp

Do we really need 3 registers in the adderexample? No, its possible to use only one ortwo registers to compute S=A+B.


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Recovery

The best way to recover is rewrite the Flash

memory with original images This require a dump of the/dev/flash/all and backup it in a safeplace (your PC)

Use netflash to cover the corrupted portionof Flash memory

In case the system cannot boot up, user canuse the JTAG cable to download the FPGAconfiguration as shown in next slices.


The Suzaku board accept MCS PROMformat for configuration

1 2Select Generate PROM, ACE, orJTAG File in Process View

Select Process

Run frommain menu

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Add top.bit in demo project

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Exit iMPACT without

saving anything

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top.mcs will be generated in the demo directory.

This file can be downloaded to Flash memory using JTAG.

Step 7: Download Configuration

The configuration file top.mcs must bedownloaded through TE7720 using JTAG

cable Make sure the JTAG cable is connected to

the CON2 port of Suzaku correctly. Download the configuration using the lbplay2

utility

..\lbplay2.exe -deb top.mcs

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