ieee journal of solid-state circuits, vol. 52, no. 1 ... · for this type of sensors is 3.2...

IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 52, NO. 1, JANUARY 2017 185

A MEMS-Assisted Temperature Sensor With20-µK Resolution, Conversion Rateof 200 S/s, and FOM of 0.04 pJK2

Meisam Heidarpour Roshan, Samira Zaliasl, Kimo Joo, Kamran Souri, Rajkumar Palwai, Lijun (Will) Chen,Amanpreet Singh, Sudhakar Pamarti, Nicholas J. Miller, Joseph C. Doll, Carl Arft, Sassan Tabatabaei,

Carl Sechen, Fellow, IEEE, Aaron Partridge, and Vinod Menon

Abstract— This paper presents a dual-microelectromechanicalsystem (MEMS) resonator-based temperature sensor. In this sen-sor, the readout circuit estimates the temperature by measuringthe frequency ratio of the two clocks generated by separateresonators with different temperature coefficients. The circuit isrealized in a 0.18-µm CMOS process and achieves a resolutionof 20 µK over a bandwidth of 100 Hz while consuming 19 mWof power, leading to a resolution FOM of 0.04 pJK2. It enablesus to implement a MEMS-based programmable oscillator withan Allan deviation of

186 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 52, NO. 1, JANUARY 2017

Fig. 1. MEMS-based programmable oscillator includes a CMOS die,a MEMS die, and a leadframe in a single package.

output clock frequency stable [Fig. 2(b)]. Therefore

Fout = Fref × (1 + TDCout) × PFM/NPdiv (2)where TDCout is a scaled output of the temperature-to-digitalconverter (TDC). This technique, however, introduces the TDCas another contributor to the output clock PN. Thus, it shouldhave enough resolution to keep its noise within the acceptablerange for the targeted clock jitter.

In this paper, a MEMS-based programmable oscillator suit-able for telecom applications is presented [1]. The refer-ence clock of the frequency synthesizer (ClkTF) is generatedby a Temp-Flat MEMS (MEMSTF) resonator operating atfTF = 47 MHz, which exhibits

HEIDARPOUR ROSHAN et al.: MEMS-ASSISTED TEMPERATURE SENSOR 187

Fig. 2. (a) MEMS-based programmable oscillator architecture in both XO and TCXO modes. (b) In a TCXO device, the output clock frequency remainsstable through multiplying the PFM value by a properly scaled TDC output.

Fig. 3. General architecture of a temperature sensor operating based on measuring the ratio of the frequencies of two oscillators with different temperaturecoefficients.

to the previous example, to avoid modal interaction betweenthe resonators through the oven, they may not be optimizedfor the best PN.

As depicted in Fig. 3, measuring the frequency ratio oftwo on-chip oscillators with different temperature sensitiv-ities is a well-known approach to realize a temperaturesensor [26]–[28]. The resolution of such a sensor is determinedby the PN of the oscillators as well as the random and/orquantization noise of the frequency ratio engine itself. Employ-ing low-jitter MEMS-generated clocks, together with a lownoise frequency ratio engine, can be considered as a solutiontoward achieving the target resolution. Therefore, besidesMEMSTF, a Temp-Sense MEMS (MEMSTS) resonator witha temperature coefficient of −7 ppm/K is also employed togenerate ClkTS, the second input clock for the frequency ratioengine, that oscillates at fTS = 45 MHz. As shown in Fig. 4,both resonators are placed next together to maximize theirthermal coupling. Each resonator includes four rings, whichare used for capacitive actuation and sensing, and coupled bycross-members [35]. Both resonators achieve a typical qualityfactor of 150 000. Their temperature sensitivities are tightlycontrolled by manipulating the mechanical properties of theresonators. In this scheme, the challenge of designing the TDCis practically narrowed down to realizing a frequency ratio

Fig. 4. 3-D view of both MEMSTF and MEMSTS resonators and the MEMSdie photo.

engine, whose output noise is dominated by the PNs of itstwo input clocks.

Fig. 5(a) illustrates the most straightforward architectureof measuring the ratio of the two frequencies. As shown,a number of cycles that are generated by the clock f1 arecounted during a gate time set by a divided version of anotherclock, i.e., f2/M [29], [30]. Therefore, the counter valuechanges proportional to the ratio of the two frequencies.


Fig. 5. (a) Reciprocal counting method. (b) Employing a time-to-digitalconverter to improve the speed of the reciprocal counting method.

However, this topology is extremely slow to achieve highresolutions. For instance, in this paper, a 50-µK change intemperature causes the ClkTS period TTS change by

!TTS ≈ 7(ppm

K

)× 50 µK × TTS × 10−6

≈ 7.78 × 10−18 s. (4)Since the smallest detectable time change by the counteris TTS, assuming a period of TTF for ClkTF, the mini-mum required conversion time Tconv to detect such smalltemperature change is given by

Tconv =TTS

!TTS×TTF ≈ 60.7 s (5)

which is impractically large and cannot be afforded in mostapplications.

As shown in Fig. 5(b), in a different approach, a TDC canbe used in order to detect the accumulated phase change by!TTS during the sensor’s full conversion time, e.g., 5 ms inthis paper, resulting in a required time resolution Tres of

Tres ≈TconvTTS

× !TTS ≈ 1.75 ps (6)

which is not easily achievable in the 0.18-µm CMOS processused in this paper. It should be noted that the resultsin (5) and (6) by themselves are optimistic as they do notconsider the noise contribution by the two clocks. A keyobservation is that in both of these approaches, the informationon all the edges of Clk1 and Clk2 is lost between the samplingpoints. From an information perspective, a loss of informationinherently translates to a reduction in performance when at thelimit of the data in the signal.

B. New Frequency Ratio Engine Architecture

As demonstrated in Fig. 6(a), a new approach is presented inthis paper, which operates based on measuring the time differ-ences !Ti between the rising edges of the two clocks, thereby

exploiting the information available on all the transition points.By passing the resulting !T sequence through an optimalfilter, the ratio between the two frequencies can be measuredwith the desired resolution and speed. The optimal filter couldbe a high-order low-pass filter or a least mean square adaptivefilter. Plotted in Fig. 6(b), this idea can be implemented byemploying a high-speed ring oscillator, followed by two-phasequantizers. Each of the phase quantizers measures the phasetravelled by the ring oscillator during every period of itsinput clock. Thus, the ratio between the output of the twoquantizers is a unit-less number, containing the frequency ratioinformation that can be extracted with the target resolutionafter proper filtering. The higher the oscillation frequency ofthe ring, the higher the resolution the time-to-digital converterachieves, thus leading to a better frequency ratio estimation.Although this topology works fine, it suffers from all thedownsides of a free running ring oscillator, e.g., frequencydrift over a long time.

Illustrated in Fig. 6(c), in order to overcome the aforemen-tioned issue, the free running ring oscillator is placed insidea phase-locked loop to lock its phase to ClkTF. Therefore,only one phase quantizer is needed for ClkTS, since ClkTFhas already been phase-locked to the ring oscillator. In thisscheme, the phase quantizer measures the phase travelled bythe ring oscillator during each ClkTS period, from which thefrequency ratio can be estimated after a proper filtering. Theperformance of this viable architecture can be further improvedby locking the ring oscillator to the scaled frequency ratioof the input clocks. As shown in Fig. 6(d), this topologyforms a new PLL with a reference of ClkTS, in which theother PLL is nested inside it, acting as a digitally controlledoscillator (DCO) for the outer loop. For this idea to work, thering oscillator must be placed inside a fractional-N PLL, asthe frequency ratio is a noninteger quantity. This topology isthe core idea of the frequency ratio engine used in this paper,leading us to measure the temperature with high resolution ina short conversion time. The key advantage of this architectureis that it extracts all the temperature information available onthe edges of the two input clocks, and in fact, that is how itenables meeting the target resolution and speed specificationssimultaneously.

III. IMPLEMENTATION

A. System Level

Fig. 7 shows the block-level architecture of the presentedfrequency ratio engine. It consists of an analog "! fractional-N PLL referenced to ClkTF, nested in a digital PLL referencedto ClkTS. Assuming a fixed fTF, the analog PLL behaves likea DCO, since its output frequency fDCO is set by the fractionaldivider input value DCOin, which is a digital number. Hence

fDCO = fTF × DCOin. (7)

On the other hand, the digital PLL employs a feedback dividervalue of 10, and thus

fDCO = fTS × 10. (8)


Fig. 6. (a) Architecture of a temperature sensor operating based on computing the frequency ratio of two clocks using a time-to-digital converter and afilter. (b) Implementing the time-to-digital converter by utilizing a ring oscillator and two-phase quantizers. (c) Ring oscillator is phase locked to ClkTF.(d) Oscillator runs at the scaled ratio of the frequencies of the input clocks.

Fig. 7. Block diagram of the presented dual-MEMS-resonator temperature sensor.

Therefore, by combining (7) and (8), the fractional dividerinput value is expressed as

DCOin =10 × fTS

fTF. (9)

The feedback loops force DCOin to be always a scaled ratioof the input clock frequencies. Thus, temperature can be readout by postprocessing the DCOin value. Similar to Fig. 5,the voltage-controlled oscillator (VCO) of the analog PLL ispart of a time-to-digital converter used in the digital phasequantizer. The higher the frequency it oscillates, the less thenoise the digital PFD injects into the loop. According tothe noise analysis described in Section IV, a divide valueof 10 makes the resolution target attainable without imposingtoo much complexity on the digital PFD, while keeping theVCO power consumption in a reasonable range. Since thistemperature sensor is aimed to compensate for the MEMSTFfrequency variation, as shown in Fig. 7, its output is prop-erly scaled to exhibit the inverse characteristic of the fTFerror across temperature. To do so, DCOin is applied to adigital block, so called TDC datapath, composed of a digitalseveth-order polynomial followed by a low-pass filter. Thepolynomial order is chosen based on the level of the non-linearity of the two resonators and the target output frequencystability. Its coefficients are also individually set for eachdevice after characterizing the resonators over temperature.

The low-pass filter cuts the noise of the TDC above thedesired BW.

B. Noise Analysis and Circuit-Level Implementation

The key target in the design of the TDC is that thefrequency ratio engine has sufficiently high BW to track rapidtemperature variation while having a negligible impact on theTDC output noise at close-in. Fig. 8 illustrates the block-level model of the frequency ratio engine shown in Fig. 7,along with the major noise sources present in the system.As introduced earlier, the digital PLL is composed of a clockdivider, a time-to-digital converter operating as a PFD, a digitalloop filter L(z), and a DCO. The digital loop filter output,which is the output of the frequency ratio engine, tracks thephase variation of ClkTS within the digital PLL BW thatoccurs due to ambient temperature fluctuation. Thus, a BWof 5 kHz is considered for this loop to ensure the engine issufficiently fast for the target temperature sensor BW. TheDCO is an analog "! fractional-N PLL that includes an XORPFD, a loop filter, a fractional divider, and a VCO. BesidesClkTF PN, the "!-modulator quantization noise as well as theVCO PN are the main contributors for the DCO output noise.In this design, a third-order "!-modulator is employed toboth reduce the in-band noise contribution of the fractionaldivider and also to increase the far-out noise power of theDCO that in practice dithers more the DCO output clock edge,


Fig. 8. Frequency-domain model of the frequency-ratio-engine.

Fig. 9. Detailed view of the major noise sources present in the system and their transfer function toward the output of the temperature sensor.

and hence improves the effective resolution of the subsequenttime-to-digital converter. Fig. 9 shows the major noise sourcesalong with their shape across frequency and transfer functiontoward the TDC output [31], in which

Adco( f ) =vdd2π

× H (s) × Kvcoj f

× 1Nnom

(10)

Gdco =Adco

1 + Adco(11)

where Adco( f ) is the analog PLL loop gain, vdd is the PFD’ssupply voltage, H (s) is the transfer function of the loop filter,Nnom is the analog PLL nominal divide value, and Gdco( f ) isa base function defined by Adco( f ). Since Adco( f ) has a low-pass behavior with a pole at the origin, Gdco( f ) also has theshape of a low-pass filter with a BW of the DCO loop fdco,around 2 MHz. The DCO transfer function can be expressedas

Hdco( f ) = fTF × Gdco( f ) ×1j f

. (12)

Similarly, the digital PLL loop gain can be found as

Atdc( f ) =TTS2π

× L(s) × Hdco( f ) ×1

Ndiv(13)

Gtdc( f ) =Atdc

1 + Atdc(14)

where L(s) is the digital loop filter transfer function in theLaplace domain, Ndiv is the divide value, which is set to 10 inthis design, and Gtdc( f ) is a base function defined by Atdc( f ).According to the definition of Atdc( f ), Gtdc( f ) has a low-passfilter shape whose BW is equal to the digital PLL BW ftdc,about 5 kHz. As far as the temperature sensor is concerned, theoutput noise power at frequencies below 100 Hz is important.Among the noise sources shown in Fig. 8, the "!-modulatornoise and the VCO PN have minimal impact on the outputnoise within that range. That is because inside the DCO,former is aggressively shaped by the modulator noise transferfunction and the latter is attenuated by a high-pass transferfunction. They both are further suppressed by the high-passtransfer function from the DCO output to the loop filter output


Fig. 10. Building blocks utilized to implement the frequency ratio engine and the TDC datapath.

Fig. 11. Digital PFD architecture, composed of a coarse and a fine section.

of the digital PLL. The ClkTF PN ∅n,TF, however, is firstamplified by Nnom within the DCO and then is attenuatedby the high-pass shape of the transfer function from the DCOto the engine output. The ClkTS PN ∅n,TS passes through thesame transfer function set by the digital PLL, while beinggained up by Ndiv as well. Since the Ndiv and Nnom valuesare very close together in steady state, it is a fair statementthat both ∅n,TS and ∅n,TF show up at the engine output withthe same gain.

The last noise source is the quantization noise of the time-to-digital converter. It is assumed to have a noise power spectraldensity of (!Teq)2/12 that goes through a transfer functionsimilar to that of ∅n,TS, but with a different dc gain. Hence,this noise has a negligible impact at very low frequencies.However, it is important to ensure it is going to stay belowthe noise contributed by the input clocks within the sensorBW. This model suggests a !Teq < 250 ps to guaranteethe minimal impact on the output noise at frequencies below100 Hz.

Fig. 10 shows the frequency ratio engine in more detail.The PFD in the digital loop, which computes the DCO phasevariation at every ClkTS period, is composed of a coarse and a

fine section. As demonstrated in Fig. 11, the coarse quantizeris a 4-b counter that continuously counts the rising edges of theVCO output, which according to (7) runs at 450 MHz in thelocked condition, and thus has a resolution of around 2.22 ns.To achieve a resolution of


Fig. 12. Chip micrograph of the MEMS-based programmable oscillator.

being added to that of the fine quantizer output. Therefore, thedigital PFD output DOUT can be expressed as

DOUT = (9 × COUT) + FOUT (15)

where COUT and FOUT are the outputs of the coarse and thefine quantizers, respectively. The VCO phase error, which isfound by subtracting DOUT from 90 steps (the desired phasetravelled by the ring in the locked condition as computed bythe digital PFD), is then fed to the digital loop filter. In fact,since the digital PLL forces the VCO phase error to be zero,this subtraction acts as a divide by 10. The digital loop filteroutput, whose coefficients are chosen for a 5-kHz BW, isapplied to the "!-modulator input of the DCO to close theloop and also to the TDC datapath for further processing andgenerating the proper correction value to compensate for theClkTF frequency error at each temperature. It is important thatthe digital circuitry has sufficient operand width, so that thetruncation errors do not dominate the TDC output noise.

IV. REALIZATION AND MEASUREMENTS

Fig. 12 shows a chip micrograph of the MEMS-basedprogrammable oscillator, in which the MEMS die is flippedand attached to a 0.18-µm CMOS die. The oscillator sus-taining circuits are placed under the MEMS die. The analogsection of the frequency ratio engine is shown as DCO inthis photo and the digital portion of the sensor is part of thechip digital block. The MEMS die carries both resonators:MEMSTF and MEMSTS. The resonators are physically placedas close as possible to maximize their thermal coupling.This is to ensure the TDC can accurately track any temper-ature fluctuations. The entire temperature sensor, includingthe MEMS die, the oscillator sustaining circuits for bothresonators, and the frequency ratio engine followed by theTDC data-path, occupies around 0.54-mm2 area and consumesabout 19 mA of current from a 1.6 V regulated supply voltage.The polynomial coefficients for each part are calculated off-chip based on ClkTF, ClkTS, and the output clock frequency

Fig. 13. Test setup for measuring the resolution of the temperature sensor.

Fig. 14. Measured PN for a 20-MHz output clock in different operationmodes as well as the estimated contribution of the temperature sensor on theoutput clock PN.

over temperature, and burned into nonvolatile memory in eachdevice.A. Resolution Measurement

In order to measure the resolution of a temperature sensor,normally, the device is encapsulated inside a thermal insulatorto bring the environmental temperature variation well belowthe expected sensor resolution. Since this TDC’s resolutionis at the tens of µK level, measuring its performance in astandalone fashion is not trivial, due to the various sourcesof on- and off-chip thermal drifts present in the measurementsetup and the climate chamber. However, in a TCXO device,as illustrated in Fig. 13, temperature variation appears as acommon-mode noise for the frequency synthesizer, and thus,it does not show up at its output clock frequency and phase.Therefore, instead of stabilizing the temperature for reliablyreading out the TDC, the output clock PN is measured toindirectly determine the TDC’s output noise spectrum.

In a proper design, however, the TDC noise is too low that itdoes not emerge at the output. As shown in Fig. 14, the PNsof the output clocks are identical for both XO and TCXOmodes, thus proving that the TDC noise does not change theoutput clock PN. To make the TDC noise measureable, thelow-pass filter in the TDC data-path was initially bypassed tomake its contribution observable in the frequency range from200 to 2 kHz. As depicted in Fig. 15(a), in order to makethe TDC noise the dominant source over the entire desired


Fig. 15. (a) Frequency stability of a TCXO device with a gained up TDC output. (b) Output clock frequency drift versus temperature for the gained upTDC.

TABLE I

PERFORMANCE COMPARISON WITH PREVIOUS BEST REPORTED TEMPERATURE SENSORS

Fig. 16. Energy/conversion versus resolution for different types of high-resolution temperature sensors.

frequency range, its contribution was amplified through a dig-ital gain stage in the TDC datapath. For the device under test,ClkTF has a temperature sensitivity of 0.9 ppm/K, requiringa slope of −0.9 ppm/K at the TDC output to ensure that

the output clock frequency remains stable. A 24-dB gain inthe TDC datapath changes this sensitivity to −15.8 ppm/K,resulting in an output frequency stability of −14.9 ppm/K.This analysis is verified by slightly varying temperature andmeasuring the output frequency, as shown in Fig. 15(b).Furthermore, the output clock PN measurement in this modealso confirms the existence of 24 dB higher noise between 200Hz and 2 kHz, which can be extended to low offset frequenciesas well. Thus, by subtracting 24 dB from this PN and applyingthe effect of the low-pass filter, which was bypassed duringthis measurement, the exact TDC contribution can be found.

This measurement precisely reveals the relationship betweenthe environmental temperature variation and the output clockfrequency and phase. Hence, the TDC’s resolution can beaccurately estimated by passing the TDC noise contributioninto this transfer function to find out its input referred noise.Accordingly, the dual-MEMS-resonator temperature sensorproves to have a resolution of 20 µK over a BW of 100 Hz,resulting in a resolution FOM of 0.04 pJK2. Compared withour previous work [1], this chip represents a 3× improvement,which results from reducing the contribution of the oscillators’sustaining circuits on the TDC output noise. This is achievedby optimizing the size of the devices used in the voltage


Fig. 17. Measurement results for MEMSTF, MEMSTS, and the output clock frequency stability for TCXO parts as well as the hysteresis test result for theoutput clock frequency of a TCXO device.

Fig. 18. ADEV measurement result for a TCXO device in both breezy andquiet environments.

regulators of the oscillators for better noise performance.It also exhibits a 16× improvement, when compared withthe state-of-the-art temperature sensor, published to date [23].Fig. 16 demonstrates the position of this work in the resolutionFOM plot along with the other high-resolution temperaturesensors. As shown, this TDC simultaneously improves boththe resolution and the temperature tracking BW. Its detailedperformance is summarized in Table I and compared withother best-in-class temperature sensors.

B. Programmable Oscillator’s Performance Measurement

Fig. 17 depicts the measured stability for both the MEMSTFand MEMSTS resonators for 30 parts over a temperature rangefrom −45 °C to 105 °C. In XO mode, the output clock

stability follows the MEMSTF stability, around ±50 ppm.However, based on the measurement result plotted in Fig. 17,the programmable oscillator in the TCXO mode successfullyachieves a stability of


is the fact that the output noise of the temperature sensoris only set by the PNs of the input clocks and not by thefrequency ratio engine, thereby offering a high resolution.In addition, this topology is robust against aging, as it operatesbased on two feedback loops that force the output to be alwaysa function of the frequencies of the input clocks. This uniquespecification makes this circuit a reliable candidate for criticalapplications like base stations, where the part must work overa long time without any drift.

REFERENCES

[1] M. H. Roshan et al., “Dual-MEMS-resonator temperature-to-digitalconverter with 40 µK resolution and FOM of 0.12 pJK2,” in IEEEISSCC Dig. Tech. Papers, Jan. 2016, pp. 200–201.

[2] WirelessUSBTM Crystal Guidelines, AN19219. [Online]. Available:http://www.cypress.com/file/134326/download

[3] Datasheet, ASTXR-12. [Online]. Available: http://www.abracon.com/Oscillators/ASTXR-12.pdf

[4] M. Wiess. (2012). Telecom Requirements for Time and Fre-quency Synchronization. [Online]. Available: http://www.gps.gov/cgsic/meetings/2012/weiss1.pdf

[5] IEEE 1588TM Telecommunications Applications. [Online]. Available:http://www.nist.gov/el/isd/ieee/upload/tutorial-telcom.pdf

[6] D. Ruffieux, F. Krummenacher, A. Pezous, and G. Spinola-Durante,“Silicon resonator based 3.2 µW real time clock with ±10 ppmfrequency accuracy,” IEEE J. Solid-State Circuits, vol. 45, no. 1,pp. 224–234, Jan. 2010.

[7] D. Ruffieux et al., “A 3.2 × 1.5 × 0.8 mm3 240 nA 1.25-to-5.5V32 kHz-DTCXO RTC module with an overall accuracy of ±1 ppm andan all-digital 0.1 ppm compensation-resolution scheme at 1 Hz,” in IEEEISSCC Dig. Tech. Papers, Jan. 2016, pp. 208–209.

[8] S. Zaliasl et al., “A 3 ppm 1.5 × 0.8 mm2 1.0 µA 32.768 kHzMEMS-based oscillator,” IEEE J. Solid-State Circuits, vol. 50, no. 1,pp. 291–302, Jan. 2015.

[9] M. H. Perrott et al., “A temperature-to-digital converter for a MEMS-based programmable oscillator with


Samira Zaliasl received the B.S. degree inelectrical and computer engineering from theUniversity of Tehran, Tehran, Iran, in 2008, andthe Ph.D. degree in electrical engineering fromOregon State University, Corvallis, OR, USA,in 2014. Her doctoral dissertation focused onarchitectural solutions for nonidealities in delta–sigma-based modulators.

She joined SiTime Corporation, Sunnyvale,CA, USA, in 2012, where she developed ana-log/mixed signal circuitry for high-performance

MEMS timing references. Since 2014, she has been with the Wear-able Health Solution Division, imec, Eindhoven, The Netherlands,developing new monitoring technology for ultralow-power biomedicalapplications.

Kimo Joo received the B.S.E.E. degree incomputer engineering from Pusan NationalUniversity, South Korea, in 1994.

Since 1994, he has been a Digital DesignEngineer with several companies. He was withSamsung Electronics, South Korea, for eightyears, where he mainly developed sigma–deltaADC/DAC for audio applications. He was also withEastman Kodak for two years in charge of imagesignal processing development for CMOS sensors.In 2011, he joined SiTime Corporation, Sunnyvale,

CA, USA, designing MEMS-based high-performance CMOS circuits fortiming reference chips. He is currently working on temperature compensationand sigma–delta modulators for fractional PLL.

Kamran Souri received his M.Sc. (cum laude)from the Electronic Instrumentation Laboratory,Delft University of Technology, in 2009. Between2009 and 2014 he was a Ph.D. candidate in thesame faculty, focusing on the design of ultra-low-power/energy-efficient CMOS smart tempera-ture sensors for RFID applications.

He is currently a Principal Circuit Designer withSiTime Corporation, Sunnyvale, CA, USA, wherehe is working on circuit design for MEMS-based(temperature-compensated) oscillators. His current

research interests include the design of low-power, energy-efficient sensorinterfaces, data converters, precision analog and reference circuits.

Dr. Souri was a recipient of the IEEE Solid-State Circuits Society Pre-Doctoral Achievement Award, 2012–2013.

Rajkumar Palwai received the M. Eng. degree fromthe Indian Institute of Science, Bengaluru, India,in 2007.

He joined Texas Instruments, Bengaluru, India,where he worked on PLLs based on LC and ringVCOs as well as high-speed pipeline ADCs. Heis currently with SiTime Corporation, Sunnyvale,CA, USA, where he is working on the developmentof high-performance and low-power fractional PLLsand MEMS-based oscillators. His current researchinterests include high-speed and precision analog

circuits in general and more specifically PLLs, oscillators, and temperature-to-digital converters.

Lijun (Will) Chen received the B.S.E.E. degreefrom Xian Jiaotong University, Xi’an, China, in1995, and the M.S.E.E. degree from TsinghuaUniversity, Beijing, China, and Oregon StateUniversity, Corvallis, OR, USA, in 1998 and 2000,respectively.

Since then, he has held analog/RF designpositions with various companies, including Xicor,Chrontel, Entropic Communications, Sigma designs,and Siport. He is currently with SiTime Corporation,Sunnyvale, CA, USA, where he is designing MEMS-

based high-performance CMOS circuits for timing reference chips.

Amanpreet Singh received the B.Tech. degree inelectronics and communication engineering fromPunjab Technical University, Jalandhar, India,and the M.S. degree in electrical and computerengineering from the Georgia Institute ofTechnology, Atlanta, GA, USA.

He has held several analog design engineeringpositions with Semtech Inc., San Jose, CA,USA, AMD Inc., Santa Clara, CA, and FreescaleSemiconductors Ltd., Noida, India. He is currentlywith SiTime Corporation, Sunnyvale, CA, where

he is working on low-power analog and high-speed drivers. His currentresearch interests include analog and digital PLLs, high-speed transceivers,and low-power data converters.

Sudhakar Pamarti received the Bachelor degreein electronics and electrical communicationengineering from IIT Kharagpur, Kharagpur,India, in 1995, and the M.S. and Ph.D. degreesin electrical engineering from the University ofCalifornia, San Diego, CA, USA, in 1999 and 2003,respectively.

He is currently an Associate Professor ofelectrical engineering with the University ofCalifornia, Los Angeles, CA, USA. He was withRambus Inc. from 2003 to 2005 and Hughes

Software Systems from 1995 to 1997 developing high-speed I/O circuits andembedded software and firmware for a wireless-in-local-loop communicationsystem.

Dr. Pamarti was a recipient of the National Science Foundation CAREERAward for developing digital signal conditioning techniques to improveanalog, mixed-signal, and radio frequency integrated circuits. He currentlyserves as an Associate Editor for the IEEE TRANSACTIONS ON CIRCUITSAND SYSTEMS I: REGULAR PAPERS.

Nicholas J. Miller received the B.S.E. degreein electrical engineering from the University ofMichigan, Ann Arbor, MI, USA, in 2003, and theM.S. and Ph.D. degrees in mechanical engineeringfrom Michigan State University, East Lansing, MI,USA, in 2007 and 2012, respectively.

He was previously a Post-Doctoral Researcherwith Carnegie Mellon University, Pittsburgh, PA,USA. He has been a MEMS DevelopmentEngineer with SiTime, Sunnyvale, CA, USA, since2013. His current research interests include nonlin-

ear dynamics in microelectromechanical resonators.

Joseph C. Doll received the B.S. degree inmechanical engineering from the University ofCalifornia, Berkeley, Berkeley, CA, USA, in 2006,and the M.S. and Ph.D. degrees in mechanicalengineering from Stanford University, Stanford, CA,USA, in 2009 and 2012, respectively. His researchwas supported by a National Science FoundationFellowship and National Defense Science and Engi-neering Graduate Fellowship.

He was a MEMS Designer with SiTime from 2012to 2016, and is currently a Sensor System Architect

with Apple.


Carl Arft received the B.S. degree in electricalengineering from Michigan TechnologicalUniversity, Houghton, MI, USA, and the M.S. andPh.D. degrees in electrical engineering from theUniversity of California, Davis, CA, USA.

He has over 15 years of experience withmicroelectromechanical systems (MEMS) researchand development. He served as a Faculty Fellowwith the University of California. He heldtechnology development roles at several opticalMEMS start-up companies, including C Speed

Corporation and Newport Opticom. He is currently a Senior Director ofSystems Engineering with SiTime Corporation, and the World Leader inMEMS-based timing devices.

Sassan Tabatabaei received the Ph.D. degree inelectrical engineering from the University of BritishColumbia, Vancouver, BC, Canada, in 2000.

He has been with SiTime for eight years. Hehas been directing circuit design with SiTime since2014, where he is responsible for IC architecturaldefinitions and development of various timing prod-ucts, including uW TCXOs for mobile as well asprecision TCXO for telecom applications. He heldexecutive and technical management positions at aseveral start-up companies before joining SiTime in

2008. He holds several US patents. His current research interests includeanalog and mixed-signal circuit design/architecture, signal integrity, timing,jitter, clocking analysis, instrumentation, and test.

Carl Sechen (F’02) received the B.E.E. degreefrom the University of Minnesota, Minneapolis,MN, USA, the M.S. degree from the MassachusettsInstitute of Technology, Cambridge, MA, USA, andthe Ph.D. degree from the University of Califor-nia, Berkeley, CA, USA, in 1975, 1977, and 1986,respectively.

He was an Assistant and then Associate Professorwith the Department of Electrical Engineering, YaleUniversity, New Haven, CT, USA, in 1986. From1992 to 2005, he was an Associate Professor and

then Professor with the Department of Electrical Engineering, University ofWashington, Seattle, WA, USA. Since 2005 he has been a Professor with theElectrical Engineering Department, University of Texas at Dallas, Richardson,TX, USA. He directs the Nanometer Design Laboratory at UT Dallas, whichincludes eight Ph.D. students. In 30 years as a Professor, he has graduated 28Ph.D. students. He has authored one book, two patents, and authored or co-authored over 180 research papers. His current research interests include thedesign and computer-aided design of digital and analog integrated circuits.

Dr. Sechen received the Distinguished Teaching Award for the Erik Jon-sson School of Engineering and Computer Science, University of Texas atDallas, 2014, the Distinguished Teacher of the Year Award, Department ofElectrical Engineering, Erik Jonsson School of Engineering and ComputerScience, University of Texas at Dallas in 2008, the Semiconductor ResearchCorporation’s Inventor’s Recognition Award in 2001 for his developmentof output prediction logic, the 1994 SRC Technical Excellence Award, theSemiconductor Research Corporation’s 1988 SRC Inventor’s Award, and theOutstanding Research Advisor Award from the Department of ElectricalEngineering, University of Washington, in 2002. He is a co-founder ofTimberWolf Systems Inc. He also received the Best Project Award from theNational Science Foundation’s Center for the Design of Digital and AnalogICs in 2002. He developed the first version of the TimberWolf placementand routing package in 1983. Versions of TimberWolf that he developed atUC Berkeley, Yale University, and the University of Washington were usedin production at more than 20 companies and were used at more than 25universities.

Aaron Partridge received the B.S., M.S., andPh.D. degrees in electrical engineering fromStanford University, Stanford, CA, USA, in 1996,1999, and 2003, respectively. His thesis wason MEMS accelerometers for the NASA X-33space plane and the first thin-film encapsulatedpiezoresistive accelerometers.

From 1987 to 1991, he was a founder and ChiefScientist of Atomis, Inc., Berkeley, CA, USA, amanufacturer of scanning tunneling microscopes,atomic force microscopes, and ballistic emission

electron microscopes. From 2001 to 2004, he was a Project Manager withthe Robert Bosch Research and Technology Center, Palo Alto, CA, USA,where he coordinated the MEMS resonator and packaging research. He iscurrently a founder and Chief Scientist of SiTime Corporation, Sunnyvale,CA, USA, where he guides the technological direction. He has authored orco-authored 30 scientific papers and holds 70 patents.

Dr. Partridge has served on the IEEE International Solid-State CircuitsConference Imagers, MEMS, Medical and Displays Subcommittee. He isthe Editorial Chair of the IEEE International Frequency Control Symposium,and is an Associate Editor of the IEEE TRANSACTIONS ON ULTRASONICS,FERROELECTRICS, AND FREQUENCY CONTROL.

Vinod Menon received the B.Tech. degree inelectrical engineering from IIT Mumbai,Mumbai, India, and the M.S. degree in electricaland computer engineering from the University ofCalifornia, Santa Barbara, CA, USA.

Since 2012, he has been an Executive VicePresident of Engineering at SiTime. He has over30 years of semiconductor industry experienceleading international IC development organizationsand delivering innovative high-value products. Hewas the VP, Serial Interface & Protocols Solutions

at LSI Corporation acquired by Avago, now Broadcom, where he ledHigh-Speed SerDes, Analog Mixed-Signal, Ethernet PHY, and Protocol IPdevelopments for 65/40/28 nm ASICs and ASSPs. Before joining LSI, hewas a Business Unit and Engineering Director with National Semiconductor(acquired by Texas Instruments), where he led the successful turnaround ofthe Interface Division and delivered multiple generations of high-performanceanalog BiCMOS and CMOS products, including precision timing solutions.He directed product developments for wired and wireless networking, andstorage connectivity at Advanced Micro Devices.

ieee journal of solid-state circuits, vol. 52, no. 1 ... · for this type of sensors is 3.2...

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