elen0040 - electronique...

ELEN0040 - Electronique numerique

Patricia ROUSSEAUX

Annee academique 2014-2015

CHAPITRE 4

Sequential circuits

ELEN0040 4 - 168

1 Fundamentals of Sequential Circuits1.1 Motivation1.2 Synchronous and Asynchronous Circuits1.3 State, State Diagram and State Table1.4 Time simulation

2 Latches

3 Flip-Flops

4 State diagrams and State Tables

5 Finite State Machine Diagrams

ELEN0040 4 - 185

Real Basic Memory Element (1bit) : the LATCH(“Verrou”)

I state = 1 binary variable = 1 bit

I capability to force output to 0 or 1

I asynchronous storage elements

I from basic to more elaborated latches :

1. basic (NOR) SR Latch2. basic (NAND) SR Latch3. clocked SR Latches4. D Latch

ELEN0040 4 - 186

Basic SR Latch

I Formed by 2 cross-coupled NOR gates

I The states are defined by outputs Q, Q which normally arereciprocally complemented values

I There are thus 2 useful states :I the Set State : Q = 1, Q = 0I the Reset State : Q = 0, Q = 1

I There are two inputs :I set input S : S = 1 brings the system in its Set stateI reset input R : R = 1 brings the system in its Reset state

ELEN0040 4 - 187

SR Latch behavior

1. start with R = 0, S = 0, the storedstate is initially unknown

2. S changes to 1, this sets Q to 1

3. S back to 0 , Q “remembers” 1thus, two input conditions causethe system to be in set state

4. R changes to 1, this resets Q to 0

5. R back to 0, now Q “remembers” 0thus, two input conditions causethe system to be in reset state

6. suppose both S and R changes to 1

7. both Q and Q are zero ! ! !,undefined state

8. if both R and S go to zerosimultaneously, can lead to unstableor “race” condition, oscillatingbetween 00 and 11 undefined states

ELEN0040 4 - 188

Timing diagram

Race conditions :

1. S = R = 1, Q = 0, Q = 0

2. S and R go simultaneously to 0

3. 1 gate delay later Q = 1, Q = 1


5. .....

ELEN0040 4 - 189

Timing diagram

Race conditions :

1. S = R = 1, Q = 0, Q = 0

2. S and R go simultaneously to 0



5. .....

In practice, it is very difficult to observe the SR Latch in the 1-1 statesince one S or R usually changes first. The latch ambiguously returns tostate 0-1 or 1-0.

ELEN0040 4 - 189

SR Latch state tableThe time behavior of the SR Latch is summarized in the state tableshowing next state based on the current inputs (S ,R) and the currentstate Q(t)

S R Q(t) Q(t + ∆)0 0 0 0 hold previous state0 0 1 10 1 0 0 reset0 1 1 01 0 0 1 set1 0 1 11 1 0 X forbidden1 1 1 X

It can also be described by the following equation :

Q(t + ∆) = S + RQ(t)

∆ is the gate delay, the time between change in input and correspondingchange in state. One usually writes Q(t + 1).

ELEN0040 4 - 190

Basic S R LatchThe cross-coupling of 2 NAND gates presents a similar behavior with :

I S = 0 to switch to set state

I R = 0 to switch to reset state

I both R = 0, S = 0 correspondsto an undefined state

S R Q(t) Q(t + ∆)1 1 0 0 hold previous state1 1 1 11 0 0 0 reset1 0 1 00 1 0 1 set0 1 1 10 0 0 X forbidden0 0 1 X

Q(t + 1) = S + RQ(t)

ELEN0040 4 - 191

Controlled SR Latch

I A control or “enable” or “clock” input C is added

I The state can only change if the control input is high

I The S , R inputs are only observed when C is high

I The behavior and the state table are exactly the same as those ofthe SR Latch (with NOR gates) when C = 1

I When C = 0, the state remains unchanged, regardless of the valuesof S and R

I The problem of the undefined state remains : C = 1, S = 1, R = 1

ELEN0040 4 - 192

D Latch

I The undefined state is removed by imposing necessarily differentvalues to inputs S and R

I To this end, an inverter is added

I There remains one input D :I D = 1 is equivalent to S = 1I D = 0 is equivalent to R = 1

ELEN0040 4 - 193

D latch : modes of operation

I When C = 0 : the latch is in its memorizing mode, the output is thememorized state

I When C = 1 : the latch is in its transparent mode, the outputfollows the input

C D Q(t) Q(t + 1)0 X 0 0 memorizing mode0 X 1 11 0 0 0 reset1 0 1 01 1 0 1 set1 1 1 1

Q(t + 1) = CQ(t) + CD

ELEN0040 4 - 194


2 Latches

3 Flip-Flops



ELEN0040 4 - 195

How to build a synchronous basic memory cell ?

I Using latches, the states can continuously change, following theirinput changes as long as the clock signal is high

I This undesired behavior for synchronous systems is linked to thefeedback path from latches outputs to latches inputs through acombinational logic circuit

I This feedback path imposes the delay of the combinational logiccircuit which computes latches inputs from present state

ELEN0040 4 - 196

The latch timing problem

I The simplest possible combinationalcircuit is an inverter

I The following simple circuit combines aD latch as memory cell and an inverteras combinational circuit

I Suppose initially Y = 0

I As long as C = 1, the value of Ycontinues to change

I The changes are based on the delaypresent in the loop through theconnection from Y to Y

I Be carefulI the memory cell used is a stable circuit since it does not include an

inverter in its internal feedback loopI the problem comes from the external loop

ELEN0040 4 - 197

Solution : the Flip-FlopI The desired behavior for synchronous clocked sequential circuits :

the state can only change once per clock pulse

I The solution is to break the closed path from the input to theoutput of the storage element

I Use Flip-Flop instead of latch

I Two types, depending on the triggering behaviorI Master-Slave Flip-¿Flop : the state change is triggered by the value

(high or low) of the clockI Edge-Triggered Flip-Flop : the state change is triggered by the

positive (from 0 to 1) or negative (from 0 to 1) edge of the clock

ELEN0040 4 - 198

S-R Master-Slave Flip-Flop

I is made of two clocked SRlatches connected in cascade

I the clock is inverted for thesecond latch

I When C = 1 :I The first latch=master latch is in its transparent modeI The input is observed from the first latch and passed to output YI The second latch=slave latch is in its memorizing modeI The past state is memorized, new state Y cannot pass to Q

I When C = 0 :I The first latch is in its memorizing modeI Any change in inputs S or R is not observed by YI The second latch is in its transparent modeI Y memorized by the first latch is passed to Q

I In both cases, the path from inputs S and R to output Q is brokenI As in SR latch, S = R = 1 is not allowed

ELEN0040 4 - 199

SR Flip-Flop : timing behavior

ELEN0040 4 - 200

The problem of “1s catching

I The inputs S and/or R are allowed to changewhile C = 1

I Suppose Q = 0, if1. S goes to 1 then back to 0 and then R goes

to 1 and back to 0 while C still at 1I Y , output of the master latch, follows and

goes to 1 and then to 0 after R = 1I finally 0 is passed to slave and Q = 0

2. S goes to 1 then back to 0 and then Rremains 0

I Y is set to 1 and does not change anymoreI 1 is passed to slave and Q = 1

I The expected behavior is that Q corresponds to the input values justbefore the clock goes to 0

I Case 1 is OK but unreliableI Case 2 does not provide the expected output since Q was zero

before the clock pulse and S and R are both zero just before theclock goes to 0

ELEN0040 4 - 201

Pulse-Triggered Flip-Flop vs. Edge-triggered Flip-Flop

I In SR Master-Slave flip-flop, any change in S , R during C = 1 istaken into account : the 1s’ catching problem

I The new state is triggered by the value of the clock

I This behavior is sometimes difficult to master : ifI delays in combinational circuits are too highI or unintentional changes occur

I Unexpected state changes can be observed

I Better use Edge-Triggered flip-flops

I The state change is triggered by the transition of the clockI positive edge-triggered flip-flop : when C goes from 0 to 1 (rising

edge)I negative edge-triggered flip-flop : when C goes from 1 to 0

ELEN0040 4 - 202

Negative Edge-Trigerred D Flip-Flop

The master clocked SR latch isreplaced by a D latch

I When C = 1 :I The input is observed from the first latch and passed to output Y as

long as C is highI The SR latch latch is in its memorizing modeI The past state is memorized, new state Y cannot pass to Q

I When C = 0 :I The SR latch is in its transparent modeI Y memorized by the D latch at the time instant just before clock

transition from 1 to 0 is passed to QI The change of the D flip-flop output is associated with value of

input D at the negative edge of the pulseI No 1s’ catching problem

ELEN0040 4 - 203

Positive Edge-Triggered D Flip-Flop

I An inverter is added to the clock input

I Q changes to the value of D applied at the positive clock edge

ELEN0040 4 - 204

Standard symbols for storage elements

ELEN0040 4 - 205

JK Flip-FlopI The behavior of the JK flip-flop is analogous to the SR master-slave

flip-flop except that J = K = 1 is allowed

I For J = K = 1, the flip-flop changes to the complemented state

I As a master slave flip-flop it has the same 1s’ catching behavior asthe SR flip-flop

I An edge-triggered JK flip-flop is preferred

I It uses an edge-triggered D flip-flop

ELEN0040 4 - 206

T Flip-Flop

I The behavior is the followingI for T = 0, no change in stateI for T = 1, change to the complemented state

I master-slave or edge-triggered

I the master-slave presents the 1s’ catching problem

I the edge-triggered is made from an edge-triggered D flip-flop

ELEN0040 4 - 207

Asynchronous direct inputs

I At power up or when needed, all or part of a sequential circuit has tobe initialized to a known state before it begins operation

I This initialization is done asynchronously, independently of theclocked behavior

I Direct R and/or S inputs are used

I They control the state of the internal latches of the flip-flop

I For example :

I 0 applied to R input resets theflip-flop to the 0 state

I 0 applied to S input sets the flip-flopto the 1 state

ELEN0040 4 - 208

Summary

The following slides summarize the essential characteristics of theflip-flops, in terms of the :

I Characteristic table : this table defines the next state of the flip-flopin terms of the flip-flop inputs and current state

I Characteristic equation : the equation that defines the next state ofthe flip-flop as a Boolean function of the flip-flop inputs and currentstate

I Excitation table : this table defines the flip-flop input variables valuesneeded to trigger a transition from the current state to the next state

ELEN0040 4 - 209

D Flip-Flop

ELEN0040 4 - 210

T Flip-Flop

ELEN0040 4 - 211

SR Flip-Flop

ELEN0040 4 - 212

JK Flip-Flop

ELEN0040 4 - 213

Flip-flop timing behavior : D, T

ELEN0040 4 - 214

Flip-flop timing behavior : SR, JK

ELEN0040 4 - 215


2 Latches

3 Flip-Flops



ELEN0040 4 - 216

Modeling of a sequential circuit

I The general model comprises a combinational circuit and a set ofbasic storage elements

I Synchronous systems :

I are driven by a clock

I use flip-flops as storage elements

I all the flip-flops must share exactly thesame clock signal

I all the flip-flops store their information atthe same time

ELEN0040 4 - 217

Moore and Mealy models

I Sequential systems are also called Finite State Machines

I Two models depending on the way outputs are obtained :

Moore Model

I The outputs are a function only ofstatesouput(t)=f(state(t))

Mealy Model

I The outputs are a function ofstates and inputsouput(t)=f(state(t),inputs(t))

ELEN0040 4 - 218

State definitionI A state remember meaningful properties of past input sequences

that are essential to predict future output valuesI Example : state A represents the fact that a sequence of two

successive “1” has occurred as the most recent past two inputsI Each of the states has be coded in binary valuesI To represent m states, we need n bits with n ≥ dlog2 meI Each bit corresponds to a state variableI A state is defined by a combination of values of the state variablesI The state is linked to the flip-flops present in the circuitI One flip flop contributes for one state variableI Example : the design of a sequential system requires 4 states

I the representation of these 4 states requires 2 bitsI 2 flip-flops and 2 state variables A and BI Four states :

I S0 : 00I S1 : 01I S2 : 10I S3 : 11

ELEN0040 4 - 219

State table and State diagramThe behavior of the system can be defined by :

I a logic diagram made of flip-flops and usual combinational gatesI the combinational part of the circuit is characterized the flip-flop

input equations : the Boolean functions that define the inputs of theflip-flops

I a State Table : similar to the truth table for combinational circuits.The state table presents

I the next state, i.e. the values of state variables at time t + 1I the values of the outputs at time t

for all possibles combinations of values of :I the present state variables, at time t andI the inputs at time t

I a State Diagram : a graphical form of the state table.I Each state is represented by a circle, with the state name insideI For each possible state transition, triggered by changes in the inputs,

an arc is drawn from the present state to the next stateI Each arc is labeled with the inputs values that cause the state

transitionI The corresponding outputs values are added to the labels or added

to the state name (Moore model)

ELEN0040 4 - 220

Example 1 : Mealy model

I input : X (t)

I Output : Y (t)

I States : defined by A(t)and B(t), the two statevariablesFour states :

I S0 : 00I S1 : 01I S2 : 10I S3 : 11

ELEN0040 4 - 221

Example 1 : flip-flop input equations and output equation

I flip-flop inputequations :

A(t + 1) = A(t)X (t) + B(t)X (t)

B(t + 1) = A(t)X (t)

I output equation :

Y (t) = X (t)B(t)+X (t)A(t)

I the D flip-flops usedindicate that input,output and state aredefined at positive edgeof the clock

ELEN0040 4 - 222

State table

or in more compact form

ELEN0040 4 - 223

State Diagram

I 4 states S0, S1, S2, S3

I one circle for each state

I 2 transitions from each state corresponding to X = 0 and X = 1

I The diagram, and thereof the problem, can be further simplified bymerging equivalent states

ELEN0040 4 - 224

Equivalent state definitionsI Two states are equivalent if their response for each possible input

sequence is an identical output sequenceI Or equivalently, two states are equivalent if their outputs produced

for each input value is identical and their next states for each inputvalue are the same or equivalent

I States S2 and S3 are equivalent, sameoutput and identical next state for X = 0and X = 1

I S2 and S3 are merged in a new state S’2

I The new state S’2 and S1 are alsoequivalent

I They are merged into new state S’1

I Finally, 2 states remain which can beimplemented using only one bit, and thusone state variable

I The system can be redesigned using onlyone flip-flop

ELEN0040 4 - 225

Example 1 : Moore and Mealy models

I The system combines Mealy and Moor modelsI in state S0, the output does not depend on the input (always 0) :

Moore modelI the output value is removed from the label on the arc and included

in S0 circleI for the other states, the output depends on the input : Mealy model

ELEN0040 4 - 226

Example 2 - Moore modelI The system is defined by its flip-flop input equation and its output

equationI inputs : X and YI output : ZI state variable : A

A(t + 1) = A(t)⊕ X (t)⊕ Y (t)

Z (t) = A(t)

ELEN0040 4 - 227


2 Latches

3 Flip-Flops



ELEN0040 4 - 228

References

I Logic and Computer Design Fundamentals, 4/E, M. Morris ManoCharles Kime , Course materialhttp ://writphotec.com/mano4/

I Cours d’electronique numerique, Aurelie Gensbittel, BertrandGranado, Universite Pierre et Marie Curiehttp ://bertrand.granado.free.fr/Licence/ue201/coursbeameranime.pdf

I Lecture notes, Course CSE370 - Introduction to Digital Design,Spring 2006, University of Washington,https ://courses.cs.washington.edu/courses/cse370/06sp/pdfs/

ELEN0040 4 - 229

ELEN0040 4 - 230

elen0040 - electronique...

Documents