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Logic and Computer Design Fundamentals
VHDL
Charles Kime & Thomas Kaminski
, .
Terms of Use(Hyperlinks are active in View Show mode)
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Course Pre-requisite: Digital Logic Design I
Numbers systems: binary, decimal, hex, octal
Binary arithmetic, logic gates, combinational logic analysisand design, logic simplification using K-maps
,
design of sequential circuits, state diagrams and state
machine design (also called FSM) Design and application of combinational and sequential
building blocks such as decoders, encoders, MUXes,
Reasonable knowledge of the above topics is assumed!
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Course Topics (Lecture and Lab)
1. Digital system design techniques, practical design issues,
, ,
memory basics (Chapters 6 to 8, 4th edition)2. Computer design fundamentals (Chapters 9 to 11, 4th
edition). Instruction set architecture, CPU design, RISC
processors, pipelining
. .
Modeling, simulation and synthesis of small digital sub-
systems using VHDL. Implementation on Altera FPGA
oar s.
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Introduction to VHDL
VHDL stands for VHSIC Hardware Description Language
There is a stee learnin curve associated with learnin a hardware
description language, especially for beginners Basic idea: written description (VHDL model) of a digital system that
You can test the functionality of a VHDL model in a simulator
Concept of testbench and Design Under Test (DUT)
Block diagram showing inputs/outputs corresponds to entity description
in VHDL
description in VHDL
HDL-based design is the standard practice in the real world, i.e.
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Introduction to VHDL
VHDL is used to model, simulate and synthesize digital
Motivation for VHDL Design Documentation: gives a clear and unambiguous description
of design. Chances of miscommunication are minimized compared
to English language description.
Modeling and simulation of designs: can try out many
implementations using different design techniques before actual
hardware implementation. This saves time and money. Also many
bugs can be discovered and fixed.
Design synthesis from VHDL description: currently a standardpractice in industry.
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Introduction to VHDL
Differences between VHDL and traditional SW
VHDL runs in simulated time (not real CPU time)
Code is simulated (executed) in a simulator not on computer
a t oug s mu ator tse runs on a computer
The notion of time delay and simulation environment
Concurrency and component netlisting (structural model)
Concurrency => just as real HW runs all the time with other HW
components, we need a way of specifying concurrent behaviour
Represent an adder running in parallel with other HW elements
VHDL supports the concept of concurrent statements or blocks ofstatements running in simulated time in contrast, statements in a
programming language such as C are executed sequentially
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Introduction to VHDL
VHDL consists of several parts organized as follows:
User packages user library
Vendor Packages vendor library
Package TEXTIO, Package Standard
VHDL language
Basic VHDL building blocks are:.
2. Architecture describes a designs functionality
3. Package stores certain frequently used functions, user defined types, etc.
4. Confi uration selects a version of desi n from a librar
5. Library contains (1) to (4)
WORK and STD are built-in libraries libraries promote sharing of
previously compiled designs; also source code need not be disclosed
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to all users
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Introduction to VHDL
A library contains a collection ofcompiled components
Package Entity Architecture A t ical se uence for s nthesizin desi ns usin VHDL
Create Model Compile Elaborate Simulate Synthesize
Might involve some iterations to fix bugs or to obtain better
VHDL is not case sensitive variable name data is treated
same as dAtA, which is same asDaTa, and so on
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VHDL Notation - 1
VHDL is:
ase nsens t ve
Based on the programming language ADA
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data types in arithmetic & other operations
Comments
-- [end of line]
List se arator:
Statement terminator: ;
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VHDL Notation - 2
Types and values
define various types and type conversions IEEE 1076 predefined types:
ype as wo va ues an
typebit_vector is an array of bits with integers as indices
type integer has values over a specified range of integers type oo ean s ,
IEEE 1164 predefined types: type std_ulogic has nine values U, X, 0, 1, Z, W, L, H, -
type std_ulogic_vector is an array of bits withnatural (non-negative) numbers as the indices
subtype std_logic is std_ulogic with definitions for
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mu t p e s gna s app e to a s ng e w re for modeling buses
subtype
X01Zisstd_logic
with the range X, 0, 1, Z
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VHDL Notation - 3
More on types
ost requent y use type: std_log c
Provides values needed for simulation, notably X and Z
Due to strong typing, essential for arithmetic operations
Requires additional packages to be used to perform type_
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VHDL Notation - 4
Constants
Binary Single bit: '0', '1'
Multiple bit: B"110001", B"11_0001"
(underline permitted for readability)
Octal O"61", O"6_1"
" " " " _
Decimal 49
Real 49E+1
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VHDL Notation - 5
Identifiers
xamp es: , B1, abc, run, stop, c_ n
Keywords
or s reserve n angauge
Cannot be used as identifiers
, , ,
Shown here in color
Shown in text in bold
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VHDL Constructs
Structural:
Describes interconnections of components (entities)
Analogous to logic diagrams or netlists
Concurrent VHDL or Dataflow:
Consists of a collection of statements and processest at execute concurrent y
Sequential VHDL:
Consists of the sequences of statements withinprocesses
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og c escr e may e com na ona or sequen a
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Signal Declaration
Signals can be viewed as "wires"
Aport declaration is a signal declaration with in or outadded
Examples: signal a, b: std_logic;
signalwidget: std_logic_vector(0 to 7);
--
signal c: std_logic_vector(2 downto 0);
-- 2 is MSB and 0 is LSB
por : n s _ og c_vec or own o ;signalproduct: std_logic_vector(0 to 31);
port (NA: out std_logic);
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Entities and Architectures
entity
Provides: the entity name, the inputs and outputs Analogous to a symbol in a block diagram
architecture
Specifies the relationships between the inputs and outputs of a design
May be a mixture of structural, concurrent and sequential VHDL.
A given entity may have multiple, different architectures.
Examples of entities and architectures follow.
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Libraries and Packages
A library typically contains VHDL code or compiled VHDLcode
Apackage consists of compiled VHDL code for multiple entities
and associated architectures
A package is stored in a library
Example: package func_prims is stored in library lcdf_vhdl
func_prims provides compiled code for the following delay-free
gates: and2, , and5, or2, or5, nand2, , nand5, nor2,, , , ,specify the number of gate inputs.
Generation of the lcdf_vhdl library and the func_primsacka e:
Generate a new library named lcdf_vhdl.
Using the lcdf_vhdl library as the "work" library, compile the filefunc_prims.vhd (available from the VHDL web page) that
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con a ns e componen , en y an arc ec ure escr p ons or epackage.
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First Example to Illustrate Entities,
Architectures and Constructs IC7283 - a 1-bit adder from a commercial IC
C1
B0
0
S0
C0
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A Structural VHDL Example (continued)
component NOR2
port(in1,in2: in std_logic;
_
end component;componentAND2
_
out1: out std_logic);
end component;
component XOR2
port(in1,in2: in std_logic;
out1: out std_logic);
end component;
signal N1,N2,N3,N4,N5,N6,N7:std_logic;
Declarations of 7 signals foruse in interconnecting the gates
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A Structural VHDL Example (continued)
begin
g0: NOT1port map (C0,N3);
Beginning of the body of the
architecture. There is an entry
,
g2: NOT1port map (N3,N6);g3: NAND2port map (A0,B0,N1);
_
gate_name keywordsport mapsignal list: (input, output) or
g5: NOR2port map (N2,N4,C1);
g6: AND2port map (N1,N3,N4);
g7: AND2port map (N1,N5,N7);
Basically, we are instantiating
components (logic gates) and
g8: XOR2port map (N6,N7,S0);
end structure;
connect ng t em toget er to
implement the logic diagram
End of architecture and
description
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VHDL Operators
Logical: and, or, nand, nor, xor, xnor, not
Relational: = = < >=
Shift: sll, srl, sla, sra, rol, ror
Form is sdt - s is for shift, d is direction (d = l is for left, d = r is for
ri ht and t is t e t = l is for lo ical and t = r is for rotate .
Adding +, -, &
&
isconcatenation
which permits one-dimensional operands to be place- - .
Example: For C_in andA(3:0), C_in & Ais equivalent to a 5-bit
register with C_in as the MSB andA(0) as the LSB.
+ -
Multiplying: * (multiply), /(divide),mod (modulus), rem
(remainder)
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Concurrent VHDL
Signal assignment
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Concurrent VHDL Example Using Boolean
E uations The entity is the same as for the structural VHDL example
architecture dataflow_1 of IC7283 is
signal N1,N2: std_logic;
begin -- The assignment statements are
-- Boolean equations.
N1
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Concurrent VHDL Example Using "with
select"
library IEEE, lcdf_vhdl;
_ _
entity IC7283_ws is
port (Z: in std_logic_vector(2 downto 0);
CS: out std_logic_vector(1 downto 0));
end IC7283_ws;architecture dataflow_2 of IC7283_ws is
begin
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Concurrent VHDL Example Using "with
select"
with Z select
CS
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Reading Assignment
Look up information on Introduction to VHDL
e.g. transport versus inertial delay
Resource materials for learning VHDL are available on
course we s e
Evita VHDL very useful multimedia tutorial on VHDL
VHDL Cookbook
Lo Carb VHDL tutorial
Study introduction to VHDL from the textbook
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