randal e. bryant
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Randal E. Bryant
Carnegie Mellon University
CS:APP
CS:APP Chapter 4CS:APP Chapter 4Computer ArchitectureComputer Architecture
SequentialSequentialImplementationImplementation
http://csapp.cs.cmu.edu
– 2 – CS:APP
Y86 Instruction SetByte 0 1 2 3 4 5
pushl rA A 0 rA F
jXX Dest 7 fn Dest
popl rA B 0 rA F
call Dest 8 0 Dest
rrmovl rA, rB 2 0 rA rB
irmovl V, rB 3 0 F rB V
rmmovl rA, D(rB) 4 0 rA rB D
mrmovl D(rB), rA 5 0 rA rB D
OPl rA, rB 6 fn rA rB
ret 9 0
nop 0 0
halt 1 0
addl 6 0
subl 6 1
andl 6 2
xorl 6 3
jmp 7 0
jle 7 1
jl 7 2
je 7 3
jne 7 4
jge 7 5
jg 7 6
– 3 – CS:APP
Computing with Logic Gates
Outputs are Boolean functions of inputs
ab out
ab out a out
out = a && b out = a || b out = !a
And Or Not
– 4 – CS:APP
Bit EqualityBit equal
a
b
eq
bool eq = (a&&b)||(!a&&!b)
– 5 – CS:APP
Word Equality
32-bit word size
b31Bit equal
a31
eq31
b30Bit equal
a30
eq30
b1Bit equal
a1
eq1
b0Bit equal
a0
eq0
Eq
=B
A
Eq
Word-Level Representation
bool Eq = (A == B)
– 6 – CS:APP
OFZFCF
OFZFCF
OFZFCF
OFZFCF
Arithmetic Logic Unit
Combinational logicContinuously responding to inputs
Control signal selects function computedCorresponding to 4 arithmetic/logical operations in Y86
Also computes values for condition codes
ALU
Y
X
X + Y
0
ALU
Y
X
X - Y
1
ALU
Y
X
X & Y
2
ALU
Y
X
X ^ Y
3
A
B
A
B
A
B
A
B
– 7 – CS:APP
Bit-Level Multiplexor
Control signal s Data signals a and b Output a when s = 1, b when s = 0
Bit MUX
b
s
a
out
bool out = (s&&a)||(!s&&b)
– 8 – CS:APP
Word Multiplexor
Select input word A or B depending on control signal s
Word-Level Representation
b31
s
a31
out31
b30
a30
out30
b0
a0
out0
int Out = [ S = 1 : A; S = 0 : B;];
s
B
AOutMUX
– 9 – CS:APP
Random-Access Memory
Stores multiple words of memoryAddress input specifies which word to read or write
Register fileHolds values of program registers %eax, %esp, etc.Register identifier serves as address
» ID 8 implies no read or write performed Multiple Ports
Can read and/or write multiple words in one cycle» Each has separate address and data input/output
Registerfile
A
B
W dstW
srcA
valA
srcB
valB
valW
Read ports Write port
Clock
– 10 – CS:APP
Building BlocksCombinational LogicCombinational Logic
Compute Boolean functions of inputs
Continuously respond to input changes
Operate on data and implement control
Storage ElementsStorage Elements Store bits Addressable memories Non-addressable registers
Registerfile
A
B
W dstW
srcA
valA
srcB
valB
valW
Clock
ALU
fun
A
B
MUX0
1
=
– 11 – CS:APP
SEQ Hardware StructureStateState
Program counter register (PC) Condition code register (CC) Register File Memories
Access same memory space Data: for reading/writing program
data Instruction: for reading
instructions
Instruction FlowInstruction Flow Read instruction at address
specified by PC Process through stages Update program counter
Instructionmemory
Instructionmemory
PCincrement
PCincrement
CCCCALUALU
Datamemory
Datamemory
Fetch
Decode
Execute
Memory
Write back
icode, ifunrA , rB
valC
Registerfile
Registerfile
A BM
E
Registerfile
Registerfile
A BM
E
PC
valP
srcA, srcBdstA, dstB
valA, valB
aluA, aluB
Bch
valE
Addr, Data
valM
PCvalE, valM
newPC
– 12 – CS:APP
SEQ StagesFetchFetch
Read instruction from instruction memory
DecodeDecode Read program registers
ExecuteExecute Compute value or address
MemoryMemory Read or write data
Write BackWrite Back Write program registers
PCPC Update program counter
Instructionmemory
Instructionmemory
PCincrement
PCincrement
CCCCALUALU
Datamemory
Datamemory
Fetch
Decode
Execute
Memory
Write back
icode, ifunrA , rB
valC
Registerfile
Registerfile
A BM
E
Registerfile
Registerfile
A BM
E
PC
valP
srcA, srcBdstA, dstB
valA, valB
aluA, aluB
Bch
valE
Addr, Data
valM
PCvalE, valM
newPC
– 13 – CS:APP
Instruction Decoding
Instruction FormatInstruction Format Instruction byte icode:ifun Optional register byte rA:rB Optional constant word valC
5 0 rA rB D
icodeifun
rArB
valC
Optional Optional
– 14 – CS:APP
Executing Arith./Logical Operation
FetchFetch Read 2 bytes
DecodeDecode Read operand registers
ExecuteExecute Perform operation Set condition codes
MemoryMemory Do nothing
Write backWrite back Update register
PC UpdatePC Update Increment PC by 2
OPl rA, rB 6 fn rA rB
– 15 – CS:APP
Stage Computation: Arith/Log. Ops
Formulate instruction execution as sequence of simple steps
Use same general form for all instructions
OPl rA, rBicode:ifun M1[PC]rA:rB M1[PC+1] valP PC+2
Fetch
Read instruction byteRead register byte Compute next PC
valA R[rA]valB R[rB]
DecodeRead operand ARead operand B
valE valB OP valASet CC
ExecutePerform ALU operationSet condition code register
Memory R[rB] valE
Writeback
Write back result
PC valPPC update Update PC
– 16 – CS:APP
Executing rmmovl
FetchFetch Read 6 bytes
DecodeDecode Read operand registers
ExecuteExecute Compute effective address
MemoryMemory Write to memory
Write backWrite back Do nothing
PC UpdatePC Update Increment PC by 6
rmmovl rA, D(rB) 4 0 rA rB D
– 17 – CS:APP
Stage Computation: rmmovl
Use ALU for address computation
rmmovl rA, D(rB)icode:ifun M1[PC]rA:rB M1[PC+1]valC M4[PC+2]valP PC+6
Fetch
Read instruction byteRead register byteRead displacement DCompute next PC
valA R[rA]valB R[rB]
DecodeRead operand ARead operand B
valE valB + valCExecute
Compute effective address
M4[valE] valAMemory Write value to memory
Writeback
PC valPPC update Update PC
– 18 – CS:APP
Executing popl
FetchFetch Read 2 bytes
DecodeDecode Read stack pointer
ExecuteExecute Increment stack pointer by 4
MemoryMemory Read from old stack pointer
Write backWrite back Update stack pointer Write result to register
PC UpdatePC Update Increment PC by 2
popl rA b 0 rA F
– 19 – CS:APP
Stage Computation: popl
Use ALU to increment stack pointer Must update two registers
Popped valueNew stack pointer
popl rAicode:ifun M1[PC]rA:rB M1[PC+1] valP PC+2
Fetch
Read instruction byteRead register byte Compute next PC
valA R[%esp]valB R [%esp]
DecodeRead stack pointerRead stack pointer
valE valB + 4Execute
Increment stack pointer
valM M4[valA]Memory Read from stack R[%esp] valER[rA] valM
Writeback
Update stack pointerWrite back result
PC valPPC update Update PC
– 20 – CS:APP
Executing Jumps
FetchFetch Read 5 bytes Increment PC by 5
DecodeDecode Do nothing
ExecuteExecute Determine whether to take
branch based on jump condition and condition codes
MemoryMemory Do nothing
Write backWrite back Do nothing
PC UpdatePC Update Set PC to Dest if branch
taken or to incremented PC if not branch
jXX Dest 7 fn Dest
XX XXfall thru:
XX XXtarget:
Not taken
Taken
– 21 – CS:APP
Stage Computation: Jumps
Compute both addresses Choose based on setting of condition codes and branch
condition
jXX Desticode:ifun M1[PC]
valC M4[PC+1]valP PC+5
Fetch
Read instruction byte
Read destination addressFall through address
Decode
Cnd Cond(CC,ifun)Execute
Take branch? Memory
Writeback
PC Cnd ? valC : valPPC update Update PC
– 22 – CS:APP
Executing call
FetchFetch Read 5 bytes Increment PC by 5
DecodeDecode Read stack pointer
ExecuteExecute Decrement stack pointer by
4
MemoryMemory Write incremented PC to
new value of stack pointer
Write backWrite back Update stack pointer
PC UpdatePC Update Set PC to Dest
call Dest 8 0 Dest
XX XXreturn:
XX XXtarget:
– 23 – CS:APP
Stage Computation: call
Use ALU to decrement stack pointer Store incremented PC
call Desticode:ifun M1[PC]
valC M4[PC+1]valP PC+5
Fetch
Read instruction byte
Read destination address Compute return point
valB R[%esp]Decode
Read stack pointervalE valB + –4
ExecuteDecrement stack pointer
M4[valE] valP Memory Write return value on stack R[%esp] valE
Writeback
Update stack pointer
PC valCPC update Set PC to destination
– 24 – CS:APP
Executing ret
FetchFetch Read 1 byte
DecodeDecode Read stack pointer
ExecuteExecute Increment stack pointer by 4
MemoryMemory Read return address from
old stack pointer
Write backWrite back Update stack pointer
PC UpdatePC Update Set PC to return address
ret 9 0
XX XXreturn:
– 25 – CS:APP
Stage Computation: ret
Use ALU to increment stack pointer Read return address from memory
reticode:ifun M1[PC]
Fetch
Read instruction byte
valA R[%esp]valB R[%esp]
DecodeRead operand stack pointerRead operand stack pointer
valE valB + 4Execute
Increment stack pointer
valM M4[valA] Memory Read return addressR[%esp] valE
Writeback
Update stack pointer
PC valMPC update Set PC to return address
– 26 – CS:APP
Computation Steps
All instructions follow same general pattern Differ in what gets computed on each step
OPl rA, rBicode:ifun M1[PC]rA:rB M1[PC+1] valP PC+2
Fetch
Read instruction byteRead register byte[Read constant word]Compute next PC
valA R[rA]valB R[rB]
DecodeRead operand ARead operand B
valE valB OP valASet CC
ExecutePerform ALU operationSet condition code register
Memory [Memory read/write] R[rB] valE
Writeback
Write back ALU result[Write back memory result]
PC valPPC update Update PC
icode,ifunrA,rBvalCvalPvalA, srcAvalB, srcBvalECond codevalMdstEdstMPC
– 27 – CS:APP
Computation Steps
All instructions follow same general pattern Differ in what gets computed on each step
call Dest
Fetch
Decode
Execute
MemoryWritebackPC update
icode,ifunrA,rBvalCvalPvalA, srcAvalB, srcBvalECond codevalMdstEdstMPC
icode:ifun M1[PC]
valC M4[PC+1]valP PC+5
valB R[%esp]valE valB + –4
M4[valE] valP R[%esp] valE PC valC
Read instruction byte[Read register byte]Read constant wordCompute next PC[Read operand A]Read operand BPerform ALU operation[Set condition code reg.][Memory read/write] [Write back ALU result]Write back memory resultUpdate PC
– 28 – CS:APP
Computed ValuesFetchFetch
icode Instruction codeifun Instruction functionrA Instr. Register ArB Instr. Register BvalC Instruction constantvalP Incremented PC
DecodeDecodesrcA Register ID AsrcB Register ID BdstE Destination Register
EdstM Destination Register
MvalA Register value AvalB Register value B
ExecuteExecute valE ALU result Cnd Condition
flag
MemoryMemory valM Value from
memory
– 29 – CS:APP
SEQ SummaryImplementationImplementation
Express every instruction as series of simple steps Follow same general flow for each instruction type Assemble registers, memories, predesigned combinational
blocks Connect with control logic
LimitationsLimitations Too slow to be practical In one cycle, must propagate through instruction memory,
register file, ALU, and data memory Would need to run clock very slowly Hardware units only active for fraction of clock cycle
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